Patents by Inventor Byeong-Gyu Roh

Byeong-Gyu Roh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Array substrate for dislay device and method of fabricating the same
    Patent number: 8329523
    Abstract: A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: December 11, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Dong Choi, Ki-Sul Cho, Hye-Young Choi, Doo-Seok Yang, Byeong-Gyu Roh
  • Array substrate for dislay device and method of fabricating the same
    Publication number: 20100289023
    Abstract: A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first
    Type: Application
    Filed: December 23, 2009
    Publication date: November 18, 2010
    Inventors: Hee-Dong Choi, Ki-Sul Cho, Hye-Young Choi, Doo-Seok Yang, Byeong-Gyu Roh