Patents by Inventor Byeonghee Son

Byeonghee Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240355883
    Abstract: A semiconductor device includes a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns, which are stacked to be spaced apart from each other; a source/drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns; and a blocking layer between the source/drain pattern and the active pattern, wherein the source/drain pattern includes a protruding side surface protruding toward the semiconductor patterns, the blocking layer includes silicon-germanium (SiGe), and a germanium concentration of the blocking layer is higher than a germanium concentration of the source/drain pattern.
    Type: Application
    Filed: October 31, 2023
    Publication date: October 24, 2024
    Inventors: Hyumin YOO, Myung Gil KANG, Dongwon KIM, Jongsu KIM, Beomjin PARK, Byeonghee SON
  • Publication number: 20240322012
    Abstract: A semiconductor device including an active region extending in a first horizontal direction, a nanosheet stack apart from the active region, a plurality of gate structures extending in a second horizontal direction and including a plurality of gate electrodes, a plurality of source/drain regions arranged on sidewalls of the gate structures, and a device isolation layer extending in a vertical direction, wherein the plurality of gate structures include a first gate structure in which a source/drain region is arranged on one sidewall and the device isolation layer is arranged on the other sidewall, and a second gate structure in which source/drain regions are arranged on both sidewalls, wherein the plurality of gate electrodes of the first gate structure include a main gate electrode positioned at the uppermost end and a plurality of sub-gate electrodes, and an internal spacer is between the device isolation layer and the plurality of sub-gate electrodes.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 26, 2024
    Inventors: Byeonghee Son, Myunggil Kang, Dongwon Kim, Jongsu Kim, Changwoo Noh, Beomjin Park