Abstract: A complex number quantization-based audio signal encoding method may comprise: estimating a scale factor for each subband of an input audio signal; performing complex magnitude scaling for each subband based on the scale factor; and performing polar quantization on a complex frequency coefficient for each subband, wherein the performing the polar quantization for each subband comprises applying two or more different magnitude quantization techniques based on the magnitude of the complex frequency coefficient scaled for each subband.

Abstract: A method, executed by a processor for compressing an audio signal in multiple layers, may comprise: (a) restoring, in a highest layer, an input audio signal as a first signal; (b) restoring, in at least one intermediate layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in the highest layer or an immediately previous intermediate layer, from the input audio signal as a second signal; and (c) restoring, in a lowest layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in an intermediate layer immediately before the lowest layer, from the input audio signal as a third signal, wherein the first signal, the second signal, and the third signal are combined to output a final restoration audio signal.

Abstract: A method for encoding an input signal using N flow blocks (N is a natural number greater than or equal to 2) and (N?1) split block(s), which is performed by a processor, may comprise: transmitting, by a k-th flow block (k is a natural number greater than or equal to 1 and less than or equal to N?1) among the N flow blocks, a k-th transformation signal obtained by transforming a received signal into a latent representation to a k-th split block among the (N?1) split block(s); splitting, by the k-th split block, the k-th transformation signal by a predetermined ratio, into a first split signal and a second split signal; transmitting, by the k-th split block, the first split signal to a (k+1)-th flow block; and quantizing a signal transformed by an N-th flow block and the second split signals using a quantization block.

Abstract: A method, executed by a processor for compressing an audio signal in multiple layers, may comprise: (a) restoring, in a highest layer, an input audio signal as a first signal; (b) restoring, in at least one intermediate layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in the highest layer or an immediately previous intermediate layer, from the input audio signal as a second signal; and (c) restoring, in a lowest layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in an intermediate layer immediately before the lowest layer, from the input audio signal as a third signal, wherein the first signal, the second signal, and the third signal are combined to output a final restoration audio signal.

Abstract: A generative adversarial network-based audio signal generation model for generating a high quality audio signal may comprise: a generator generating an audio signal with an external input; a harmonic-percussive separation model separating the generated audio signal into a harmonic component signal and a percussive component signal; and at least one discriminator evaluating whether each of the harmonic component signal and the percussive component signal is real or fake.

Abstract: Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.

Abstract: Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.

Abstract: An exposure apparatus of a semiconductor device may include an exposure light source; an asymmetric adjustment filter for asymmetrically adjusting intensity of a light which passes through the exposure light source; a photomask for passing the light of which intensity is adjusted by the asymmetric adjustment filter; a projection lens for projecting the light passing through the photomask; and a wafer stage for mounting a wafer on which an image is formed by the light from the projection lens.

Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.

Abstract: An exposure apparatus of a semiconductor device may include an exposure light source; an asymmetric adjustment filter for asymmetrically adjusting intensity of a light which passes through the exposure light source; a photomask for passing the light of which intensity is adjusted by the asymmetric adjustment filter; a projection lens for projecting the light passing through the photomask; and a wafer stage for mounting a wafer on which an image is formed by the light from the projection lens.

Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.

Abstract: A substrate includes an overlay vernier key structure that includes an outer pattern formed over one layer over a semiconductor substrate, as a reference for an overlay measurement, and an inner pattern comprising a cluster of vernier patterns formed over another layer.

Abstract: The present invention relates to a process for preparing a polyethylene naphthalate possessed with high viscosity, characterized by sloving of various problems of the prior art by controlling the rate of the polycondensation reaction.Particularly, the present invention provides a process for preparing polyethylene naphthalate from an esterification reaction product of naphtalene dicarboxylic acid or an alkyl ester thereof and a diol, which comprises polycondensing the esterification reaction product in the presence of a polycondensation catalyst in two steps wherein the first step is carried out at a pressure ranging from 500 to 30 torr and the second step is carried out at a pressure ranging from 10 to 0.1 torr with controlling the reaction rate such that the differential increase of the intrinsic viscosity of the resultant polymer can satisfy the following equations:IV(t.sub.1)-IV(t.sub.0)<0.4 dl/g (1)IV(t.sub.2)-IV(t.sub.0)>0.3 dl/g (2)wherein: IV(t.sub.

Abstract: The present invention relates to a biaxially oriented polyester film comprising a metallic alkylbenzene sulfonate derivative of formula(I), polyethylene glycol and, optionally, bis(4-.beta.-hydroxyalkoxyphenyl) sulfones of formula(II), which has improved antistatic property, clarity, mechanical properties and heat resistance: ##STR1## wherein: R represents an optionally substituted C.sub.8-25 alkyl group;M represents an alkali or alkali earth metal;m is an integer of 100 or fewer; andn is an integer from 1 to 10.