Abstract: An audio signal encoding/decoding method and an apparatus for performing the same are disclosed. The audio signal encoding method includes obtaining a full-band input signal, extracting a first feature vector corresponding to a first sub-band signal and a second feature vector corresponding to a second sub-band signal using an encoder neural network including a plurality of encoding layers, generating a first code vector corresponding to the first feature vector and a second code vector corresponding to the second feature vector by compressing the first feature vector and the second feature vector, and generating a bitstream by quantizing the first code vector and the second code vector.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: The present invention is provided with a delay unit for applying a function of a double-pole contact switch and a control function of an activation switch, so as for the contact switch and the activation switch not to operate simultaneously when turned on. Accordingly, when a predetermined time elapses after the double-pole contact switch operates first to prevent an inrush current shock, the activation switch generates a control signal to safely operate an internal circuit such as a central processing device or a control device, so that an electronic product is turned on without an electrical shock or a significant spark. Moreover, if power is cut off by software or the internal circuit is turned off in response to a control signal of the activation switch after an ON button of the electronic product is pressed, the double-pole contact switch is automatically turned off immediately or over a time interval, so that standby power is cut off completely, safely, conveniently, and effectively.

Abstract: The present invention is provided with a delay unit for applying a function of a double-pole contact switch and a control function of an activation switch, so as for the contact switch and the activation switch not to operate simultaneously when turned on. Accordingly, when a predetermined time elapses after the double-pole contact switch operates first to prevent an inrush current shock, the activation switch generates a control signal to safely operate an internal circuit such as a central processing device or a control device, so that an electronic product is turned on without an electrical shock or a significant spark. Moreover, if power is cut off by software or the internal circuit is turned off in response to a control signal of the activation switch after an ON button of the electronic product is pressed, the double-pole contact switch is automatically turned off immediately or over a time interval, so that standby power is cut off completely, safely, conveniently, and effectively.