Abstract: Provided is an apparatus for measuring implant osseointegration, and the apparatus for measuring implant osseointegration includes: a vibration generation unit configured to apply multiple vibrations with frequencies in different bands, respectively, to an implant fixture; a vibration sensor configured to measure three-axis vibration information of the implant fixture caused by the vibrations from the vibration generation unit; and a control unit configured to determine the degree of osseointegration based on the measured vibration information.

Abstract: The present disclosure provides a solidifying method of a radionuclide. The solidifying method of the radionuclide includes operations of: providing a low melting point glass including Bi2O3, B2O3, ZnO and SiO2; providing a glass mixture mixing a mixture to be treated containing a hydroxide of radionuclide and BaSO4 and the low melting point glass; and heating the glass mixture.

Abstract: The present disclosure provides a solidifying method of a radionuclide. The solidifying method of the radionuclide includes operations of: providing a low melting point glass including Bi2O3, B2O3, ZnO and SiO2; providing a glass mixture mixing a mixture to be treated containing a hydroxide of radionuclide and BaSO4 and the low melting point glass; and heating the glass mixture.

Abstract: Provided is an apparatus for measuring implant osseointegration, and the apparatus for measuring implant osseointegration includes: a vibration generation unit configured to apply multiple vibrations with frequencies in different bands, respectively, to an implant fixture; a vibration sensor configured to measure three-axis vibration information of the implant fixture caused by the vibrations from the vibration generation unit; and a control unit configured to determine the degree of osseointegration based on the measured vibration information.

Abstract: In a vertical dynamic memory cell, monocrystalline semiconductor material of improved quality is provided for the channel of an access transistor by lateral epitaxial growth over an insulator material (which complements the capacitor dielectric in completely surrounding the storage node except at a contact connection structure, preferably of metal, from the access transistor to the storage node electrode) and etching away a region of the lateral epitaxial growth including a location where crystal lattice dislocations are most likely to occur; both of which features serve to reduce or avoid leakage of charge from the storage node. An isolation structure can be provided in the etched region such that space is provided for connections to various portions of a memory cell array.

Abstract: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Abstract: Embodiments herein present a method for forming a poly filled substrate contact on a SOI structure. The method forms an insulator on a substrate and forms a substrate contact hole within the insulator. The insulator surface level is higher than final structure. Next, a poly overfill is performed, comprising filling the substrate contact hole with polysilicon and covering the insulator with the polysilicon. Specifically, the thickness of the polysilicon is greater than the size of the substrate contact hole. Following this, the polysilicon is etched, wherein a portion of the polysilicon is removed, and wherein the substrate contact hole is left partially filled with the polysilicon. Further, the etching of the polysilicon forms a concave recess within a top portion of the polysilicon. The etching of said polysilicon does not contact the substrate. The excess of insulator is polished off to the desired level.

Abstract: A monolithic air conditioner includes a cabinet, an outdoor heat exchanger mounted on a rear-inner portion of the cabinet and spaced away from a sidewall of the cabinet, a guide member attached on a rear surface of the outdoor heat exchanger, and a fan assembly disposed in the cabinet to introduce the outdoor air The guide member has an air exhausting guide unit and an air introduction guide unit extending from the air exhausting guide section.

Abstract: The present invention relates to a method and apparatus for securing a space for recording video, e.g., a broadcast program on a recording medium. When distribution of empty spaces scattered in a recording medium satisfies a particular condition, e.g., whether the size of a deleted program or the size of the entire empty space can accommodate video signals of a prescribed recording hours or whether the size of the empty space located at the last position is smaller than the size of all of the remaining empty spaces, the present invention moves and records recorded programs scattered in a recording medium to be continuous with one another, thereby making empty spaces scattered in the recording medium a single continuous empty space.

Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Abstract: A method for fabricating an in-plane switching LCD device includes forming a data line and a light-shielding layer on a substrate, forming a pixel electrode line and an active region with a polycrystalline silicon thin film, forming a first insulating layer on the substrate, forming a gate electrode and a common electrode line on the first insulating layer, forming a second insulating layer on the substrate, forming a first contact hole that exposes at least portions of the data line and the active region, and forming a connection electrode that connects at least portions of the exposed data line and the active region.

Abstract: Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.

Abstract: The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack comprising at least a gate dielectric and a gate polySi located on another portion of the strained Si layer; and a raised trench oxide region surrounding the active device region. The present invention also provides a method of forming such a structure. In the inventive method, the gate dielectric is formed prior to trench isolation formation thereby avoiding many of the problems associated with prior art processes in which the trench oxide is formed prior to gate dielectric formation.

Abstract: An organic light-emitting device includes a first transistor for applying a data voltage; a second transistor for applying a driving current depending on the data voltage and an initiation voltage to an organic light-emitting diode; a third transistor for generating a threshold voltage; a fourth transistor for applying an initiation voltage, the fourth transistor being connected to the third transistor; a fifth transistor for applying a power voltage; and a condenser provided between a first node connected to the third and fifth transistors and a second node connected to the first and second transistors, for maintaining the power voltage and the threshold voltage for compensation.

Abstract: An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.

Abstract: An integrated type optical coupling device capable of easily accurately performing an optical arrangement between a narrow-pitch multi-channel optical waveguide and an optical fiber array and a master used in fabricating the same are provided. By forming a fixing projection between the optical fibers, the dynamic stability of the optical fiber array is increased and the optical arrangement between the optical waveguide and the optical fiber is easily accurately performed by hand. Accordingly, the cost required for the alignment is reduced and the alignment error due to the rolling of the optical fiber is not generated. In addition, the multi-step metal master is fabricated by using a photoresist film for X-ray exposure, and the narrow-pitch multi-channel optical coupling device is fabricated in a hot embossing method using the same, thereby the high-integrated device can be fabricated at a low price.

Abstract: A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

Abstract: The present invention relates to an apparatus for preventing slipping of a vehicle on a slope, having a brake hydraulic circuit between a master cylinder and a wheel cylinder, whereby brake hydraulic pressure of the brake continues its operation on the wheel cylinder even when a driver releases a brake pedal.

Abstract: A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.