Abstract: Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

Abstract: Nonvolatile memory devices and methods of fabricating the same are provided. In some embodiments, a nonvolatile memory device includes a lower conductive member formed on an upper part of or inside a substrate, a ferroelectric organic layer formed on the lower conductive member, a protective layer formed on the ferroelectric organic layer, and an upper conductive member formed on the protective layer to cross the lower conductive member.

Abstract: First nanowires and second nanowires are alternately disposed and spaced apart on a first substrate in a second direction that is parallel to an adjacent major surface of the first substrate. Each of the first and second nanowires extends in a first direction that is perpendicular to the second direction, and the first and second nanowires are doped with first and second conductive types, respectively.

Abstract: Provided is a ferroelectric memory device. The ferroelectric memory device includes an inorganic channel pattern on a substrate, a source electrode and a drain electrode spaced apart from each other on the substrate and contacting the inorganic channel pattern, a gate electrode disposed adjacent to the inorganic channel pattern, and an organic ferroelectric layer interposed between the inorganic channel pattern and the gate electrode.

Abstract: Methods of fabricating a memory unit are provided including forming a plurality of first nanowire structures, each of which includes a first nanowire extending in a first direction parallel to the first substrate and a first electrode layer enclosing the first nanowire, on a first substrate. The first electrode layers are partially removed to form first electrodes beneath the first nanowires. A first insulation layer filling up spaces between structures, each of which includes the first nanowire and the first electrode, is formed on the first substrate. A second electrode layer is formed on the first nanowires and the first insulation layer. A plurality of second nanowires is formed on the second electrode layer, each of which extends in a second direction perpendicular to the first direction. The second electrode layer is partially etched using the second nanowires as an etching mask to form a plurality of second electrodes.

Abstract: Example embodiments relate to a biosensor using a nanoscale material as a channel of a transistor and a method of fabricating the same. A biosensor according to example embodiments may include a plurality of insulating films. A first signal line and a second signal line may be interposed between the plurality of insulating films. A semiconductor nanostructure may be disposed on the plurality of insulating films, the semiconductor nanostructure having a first side electrically connected to the first signal line and a second side electrically connected to the second signal line. A plurality of probes may be coupled to the semiconductor nanostructure. A biosensor according to example embodiments may have a reduced analysis time.

Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Abstract: Provided is a polymer memory device and a method of forming the same. The polymer memory device may include a first electrode, a first curable polymer layer, a second electrode, a second curable polymer layer, and a third electrode. The first electrode may be disposed on a substrate. The first curable polymer layer may cover the first electrode. The second electrode may be disposed on the first curable polymer layer and cross over the first electrode. The second curable polymer layer may cover the second electrode. The third electrode may be disposed on the second curable polymer layer and cross over the second electrode. Each of the first curable polymer layer and the second curable polymer layer may contain a fullerene or a fullerene derivative.

Abstract: A semiconductor memory device and a method of forming the same are disclosed. The semiconductor memory device may include a first electrode. A monolayer is coupled to the first electrode. An organic memory layer is coupled to the monolayer. A second electrode is coupled to the organic memory layer.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: An organic memory device may include a stack of an organic material layer and a fullerene layer to provide a data storage element between first and second electrodes. The data storage element may include an organic material layer formed on the first electrode, and a fullerene layer between the organic material layer and the second electrode. Methods of fabricating organic memory devices are also discussed.

Abstract: A non-volatile organic resistance memory device including a first electrode, a second electrode, and a polyimide layer interposed between the first and second electrodes. The polyimide layer has a thickness such that a resistance of the polyimide layer varies in accordance with a potential difference between the first and second electrodes.

Abstract: A resistive memory cell employs a photoimageable switchable material, which is patternable by actinic irradiation and is reversibly switchable between distinguishable resistance states, as a memory element. Thus, the photoimageable switchable material is directly patterned by the actinic irradiation so that it is possible to fabricate the resistive memory cell through simple processes, and avoiding ashing and stripping steps.

Abstract: A phase changeable memory cell is provided. The phase changeable memory cell includes a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive plug passing through the lower interlayer dielectric layer. The lower conductive plug is in contact with a phase change material pattern disposed on the lower interlayer dielectric layer. The phase change material pattern and the lower interlayer dielectric layer are covered with an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern, which is disposed in a plate line contact hole passing through the upper interlayer dielectric layer. Methods of fabricating the phase changeable memory cell is also provided.

Abstract: In a phase changeable memory device and a method of formation thereof, the phase changeable memory device comprises: a lower electrode pattern on an interlayer insulating layer; an insulating pattern located on the lower electrode pattern; a phase changeable pattern penetrating the insulating pattern and the lower electrode pattern to contact the lower electrode pattern and the interlayer insulating layer; and an upper electrode on the phase changeable pattern.

Abstract: In fabricating a phase changeable memory device, an insulating layer with an opening extending therethrough is formed on a substrate. A conductive structure is formed in the opening. The conductive structure includes a first conductive plug on opposing sidewalls of the opening and a surface therebetween and a second plug on the first conductive plug. The first conductive plug is between the second plug and the sidewalls of the opening and between the second plug and the surface therebetween. A lower electrode is formed on the first conductive plug, on the second plug, and on the insulating layer. The lower electrode extends outside the opening in the insulating layer. A phase changeable material layer is formed on the lower electrode, and an upper electrode is formed on the phase changeable material layer opposite the lower electrode.

Abstract: Methods of forming a phase-change random access memory (PRAM) include forming a lower electrode layer and a node insulating layer on an active region of a semiconductor substrate. A photoresist pattern is formed on the node insulating layer that includes an opening therein. A polymer layer is formed on the photoresist pattern and the node insulating layer. The polymer layer is etched using the photoresist pattern as an etching mask to expose the node insulating layer while leaving a portion of the polymer layer after etching on a top surface of the exposed node insulating layer and on a sidewall of the opening of the photoresist pattern. The node insulating layer is etched using the photoresist pattern and the polymer layer as an etching mask to form a confined contact hole extending through the node insulating layer to contact the lower electrode layer while forming a polymer layer on a sidewall of the confined contact hole as a byproduct of etching the node insulating layer.

Abstract: Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

Abstract: A computer simulation method for a semiconductor device manufacturing process, includes: a first step for forming an initial section of the material with only open cells exposed to the growth or etching among the cells; a second step for inputting information including growth or etching points into each open cell; a third step for computing a movement speed for the growth or etching points; a fourth step for moving the growth or etching points for a time determined according to the movement speed; and a fifth step for forming a new etching section by re-arranging the open cells exposed to the growth or etching, after moving the growth or etching points, the second to fifth steps being repeatedly performed on the re-arranged open cells until the sum of the predetermined time reaches the time (T).