Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: A semiconductor integrated circuit is provided, including: a first switch circuit; a logic circuit, coupled to the first switch circuit, a first floating diffusion point being defined between the first switch circuit and the logic circuit; a second switch circuit, coupled to the logic circuit, a second floating diffusion point being defined between the second switch circuit and the logic circuit; and a voltage holding circuit, coupled to the first floating diffusion point and the second floating diffusion point, and used to adjust the voltages of the floating diffusion points. The voltage holding circuit increases or decreases the voltage values of the first floating diffusion point and the second floating diffusion point. Thereby, the influence of long recovery time on the semiconductor integrated circuit is improved, and the stability is ensured.

Abstract: A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.

Abstract: Discussed is a battery pack that may include at least one battery module including at least one battery cell; a case tray configured to support the at least one battery module; a tray cover coupled to the case tray; and at least one bushing gasket configured to connect the case tray and the tray cover and to support the case tray on a plurality of points.

Abstract: The present invention relates to a signal synchronization adjustment method and a signal synchronization adjustment circuit, for applying to data reading according to a reference clock signal between a memory controller and a dynamic random access memory in an electronic device. First, the memory controller triggers a command signal to the dynamic random access memory; then, the dynamic random access memory delays for a column selection signal latency time according to a first rising edge of the reference clock signal, and then triggers a column selection signal; after that, the dynamic random access memory delays for an internal data strobe signal latency time, and then triggers an internal data strobe signal; finally, the dynamic random access memory delays for an external data strobe signal latency time, and then triggers an external data strobe signal. The signal synchronization adjustment circuit is applied to the signal synchronization adjustment method.

Abstract: A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

Abstract: Provided is a memory device, including a plurality of memory banks. Each of the memory banks includes a memory array and a driver circuit. The driver circuit is coupled to the memory array, arranged to operably write data to the memory array according to write signals. The driver circuit includes a plurality of row driver circuits each coupled to a row of the memory cells. A global driver power circuit coupled to the row driver circuits in the plurality of memory banks to provide a global driver power. Each of the memory banks further includes a local driver power circuit coupled to respective row driver circuits in each of the memory banks to provide a local driver power. The local driver power circuit includes a first P-type MTCMOS coupled to a supply voltage and a control signal, controlled by the control signal to provide a local multi-threshold power signal to the respective row driver circuits.

Abstract: Discussed is a battery that may include at least one battery module including at least one battery cell, a case tray configured to support the at least one battery module, a case cover coupled with the case tray to cover the at least one battery module, a sealing gasket disposed between the case tray and the case cover to prevent penetration of moisture or foreign substance into the at least one battery module, and a reinforcing unit provided to the case cover to be disposed adjacent to the sealing gasket and configured to prevent twisting of the case cover when the case tray and the case cover are coupled.

Abstract: Discussed is a battery pack that may include at least one battery module including at least one battery cell; a case tray configured to support the at least one battery module; a tray cover coupled to the case tray; and at least one bushing gasket configured to connect the case tray and the tray cover and to support the case tray on a plurality of points.

Abstract: A battery pack assembly guide jig for guiding an assembly of a battery pack having a case tray and a case cover is provided. The battery pack assembly jig includes a first guide configured to temporarily fix a first side edge of the case tray and a first side edge of the case cover, and a second guide spaced apart from the first guide by a predetermined distance and configured to temporarily fix a second side edge of the case tray opposite the first side edge of the case tray and a second side edge of the case cover opposite the first side edge of the case cover. The battery pack assembly guide jig is configured to support the case tray and the case cover of the battery pack when the case tray and the case cover are coupled to each other.

Abstract: A coolant port assembly includes a coolant port including a port portion having a pipe shape formed to extend by a predetermined length, and a plate-shaped mounting bracket portion formed at one side of an outer circumference of the port portion to expand in a direction intersecting a longitudinal direction of the port portion; a sealing gasket provided in a ring shape that surrounds a peripheral outer side of the port portion; and a gasket cover configured to be closely coupled to the mounting bracket portion together with the sealing gasket while pressing a part of the sealing gasket.

Abstract: A battery module, a battery pack including the same, and a vehicle including the same are provided. The battery module includes a stack of battery cells; a cover accommodating the stack of battery cells; and a bus bar electrically connecting the battery cells; a relay comprising a connection terminal coupled to the bus bar; and a joint block coupled to the bus bar and the connection terminal of the relay.

Abstract: A battery pack has improved safety against external impacts, and an energy storage system and a vehicle including the same. The battery pack includes a battery module having at least one battery cell; a tray having a plate shape so that the battery module is mounted thereon; a reinforcing member having a plate shape and mounted on the tray, the reinforcing member having at least a portion coupled to the tray and the other portion supporting the battery module upward, the reinforcing member being configured to form a space separated from the tray below the other portion supporting the battery module; and an elastic member constrained in the separated space in an elastically deformed state and configured to press a lower surface of the reinforcing member upward.

Abstract: A battery pack having at least one battery module including at least one battery cell, a case tray configured to support the at least one battery module, a case cover coupled to the case tray such that the at least one battery module is located between the case tray and the case cover, and a sealing gasket disposed between the case tray and the case cover to prevent penetration of moisture or foreign substances into the battery module is provided. The sealing gasket includes at least one position guide configured to guide positioning of the sealing gasket between the case tray and the case cover when the case tray and the case cover are coupled to each other.

Abstract: A data-based nuclear power plant design basis management system and a method therefor are disclosed. According to an embodiment of the present invention, the data-based nuclear power plant design basis management system comprises a database for storing: information on a plurality of design basis for defining a design basis document for configuration management in a nuclear power plant; information on a category, corresponding to each of the design basis, among a plurality of categories; and an associative relationship between the plurality of design basis, wherein the plurality of categories includes design requirements (REQ), at least one design basis specification (DBS) for satisfying the REQ, and the like.

Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.

Abstract: A data-based nuclear power plant design basis management system and a method therefor are disclosed. According to an embodiment of the present invention, the data-based nuclear power plant design basis management system comprises a database for storing: information on a plurality of design basis for defining a design basis document for configuration management in a nuclear power plant; information on a category, corresponding to each of the design basis, among a plurality of categories; and an associative relationship between the plurality of design basis, wherein the plurality of categories includes design requirements (REQ), at least one design basis specification (DBS) for satisfying the REQ, and the like.

Abstract: Disclosed is a method for providing a user interface for a game. An embodiment comprises the steps of: defining a game progress panel user interface area for displaying visual information on a game progress at one side of a display of a user terminal; defining a card panel user interface area for displaying, at the other side of the display, a card information matrix configured on the basis of card information included in an account of a game player; displaying a game character corresponding to the card information in the game progress panel user interface area on the basis of an input of the card information included in the card information matrix; and displaying the card information in an area defined around the game character.