Patents by Inventor Byeong-yun Kim

Byeong-yun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11686772
    Abstract: The present invention relates to a self-diagnostic apparatus capable of improving safety of a device under test (DUT) by analyzing a characteristic change of a DUT, such as a semiconductor, a circuit module, or a system, in a safe operating region over time and allowing a regular test and a periodic test to be performed even while the DUT is running.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: June 27, 2023
    Assignee: PhosPhil Inc.
    Inventors: Byung Kyu Kim, Byeong Yun Kim
  • Publication number: 20220137130
    Abstract: The present invention relates to a self diagnostic apparatus for an electronic device, which includes a vector memory configured to store a test function code for testing a device under test (DUT) equipped with a plurality of cores which perform arithmetic operations, a function test expected value corresponding to a function test according to the test function code, a design for test (DFT) test code, a DFT test expected value corresponding to a DFT test according to the DFT test code, and a non-test function code for a general arithmetic operation or an operation of the DUT; a test data storage configured to store test data including a DFT test code result value which is a result of the DFT test according to the DFT test code, a test function code result value which is a result of the function test according to the test function code, and a non-test function code result value which is a result of the function test according to the non-test function code; and a safety region test controller configured to sele
    Type: Application
    Filed: October 7, 2021
    Publication date: May 5, 2022
    Applicant: PhosPhil Inc.
    Inventors: Byung Kyu KIM, Byeong Yun KIM
  • Patent number: 11320483
    Abstract: Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: May 3, 2022
    Assignee: PHOSPHIL INC.
    Inventors: Byung Kyu Kim, Byeong Yun Kim
  • Publication number: 20210255241
    Abstract: Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.
    Type: Application
    Filed: August 4, 2020
    Publication date: August 19, 2021
    Inventors: Byung Kyu KIM, Byeong Yun KIM
  • Publication number: 20200393509
    Abstract: Provided is a measuring method for testing a device under test (DUT) having a plurality of terminals and, particularly, to a means for measuring the functions and performance of various electronic devices in which an electronic circuit such as that in an electronic device, a semiconductor element, a circuit module, and a circuit board is mounted, and to: a method by which a processor supports measurement with software such that unit costs can be reduced to be lower than those of conventional means operating with various, high-cost hardware; and a device using the same.
    Type: Application
    Filed: June 7, 2018
    Publication date: December 17, 2020
    Inventors: Byung Kyu KIM, Byeong Yun KIM
  • Patent number: 7706198
    Abstract: There is provided a repair method of a multi-chip that comprises a plurality of memory chips, each of the memory chips storing information with respect to remaining redundancy cells after repairing at a chip level. The repair method includes testing one of the plurality of memory chips; when the tested memory chip is judged to be defective, checking whether the tested memory chip is repairable, based on the stored information of the remaining redundancy cells; and when the tested memory chip is judged to be repairable, repairing the tested memory chip.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: April 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kook Jeong, Byeong-Yun Kim
  • Patent number: 7429794
    Abstract: In a multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip, in the case where not only a logic circuit of a first chip but also a logic circuit of a second chip requires an input signal, the multi-chip packaged integrated circuit device transmits the input signal to one or both of the logic circuits of the first and second chips via a synchronizer. In a case where three or more chips are integrated into the multi-chip packaged integrated circuit device, the input signal can be selectively transmitted to one or more of the three or more chips via the synchronizer.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: September 30, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-su Ryu, Byeong-yun Kim, Young-dae Kim
  • Publication number: 20080080275
    Abstract: In accordance with aspects of the present invention, there is provided a repair method of a multi-chip that comprises a plurality of memory chips, each of the memory chips storing information with respect to remaining redundancy cells after repairing at a chip level. The repair method includes testing one of the plurality of memory chips; when the tested memory chip is judged to be defective, checking whether the tested memory chip is repairable, based on the stored information of the remaining redundancy cells; and when the tested memory chip is judged to be repairable, repairing the tested memory chip.
    Type: Application
    Filed: September 26, 2007
    Publication date: April 3, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jin-Kook Jeong, Byeong-Yun Kim
  • Publication number: 20070152316
    Abstract: Provided is an interposer pattern having a conductive material for forming a pad chain that can reduce a wafer test time. The interposer pattern includes one or more interposers and an external conductive material for the pad chain. Each of the interposers includes a plurality of pad pairs internally interconnected. The external conductive material is disposed at external sides of the interposers to interconnect the pad pairs of one of the interposers or to interconnect at least two of the interposers. The external conductive material can be disposed at scribe lanes of a wafer.
    Type: Application
    Filed: January 3, 2007
    Publication date: July 5, 2007
    Inventors: Jung-su Ryu, Byeong-yun Kim
  • Publication number: 20070018300
    Abstract: Provided is an apparatus and method for a testing multi-stack integrated circuit package. The apparatus may include a vacuum pump and a socket. The socket may include a plurality of internal pins, a plurality of external pins, a socket body, and at least one first air inlet. The plurality of external pins may be electrically connected to the plurality of internal pins. The at least one first air inlet may communicate with the atmosphere between the plurality of internal pins. When the multi-stack integrated circuit package including a plurality of packages is tested, a plurality of package pins of the multi-stack integrated circuit package may be inserted (or placed) into the plurality of internal pins of the socket. The multi-stack integrated circuit package may be pulled (or positioned) by applying a vacuum through the first air inlet of the socket using the vacuum pump.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 25, 2007
    Inventors: Jung-su Ryu, Byeong-yun Kim, Yeon-keun Chung, Hyun-soo Park
  • Publication number: 20050280165
    Abstract: In a multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip, in the case where not only a logic circuit of a first chip but also a logic circuit of a second chip requires an input signal, the multi-chip packaged integrated circuit device transmits the input signal to one or both of the logic circuits of the first and second chips via a synchronizer. In a case where three or more chips are integrated into the multi-chip packaged integrated circuit device, the input signal can be selectively transmitted to one or more of the three or more chips via the synchronizer.
    Type: Application
    Filed: June 21, 2005
    Publication date: December 22, 2005
    Inventors: Jung-su Ryu, Byeong-yun Kim, Young-dae Kim
  • Publication number: 20050052799
    Abstract: An ESD (electrostatic discharge) circuit embedded in an SIP (system-in-package) chip using a plurality of power sources is provided. The SIP chip includes: a first chip having a first electrostatic discharge protecting circuit between a first power voltage and a first ground voltage; a second chip having a second ESD protecting circuit between a second power voltage and a second ground voltage; a first coupling diode unit having a plurality of diodes which are serially connected between the first power voltage and the second power voltage in a bidirectional manner; and a second coupling diode unit having a plurality of diodes which are serially connected between the first ground voltage and the second ground voltage in a bidirectional manner, so that the ESD stress applied to each chip can sink to the power source in the corresponding chip and the other power sources in the other chip by connecting different power sources in the SIP chip through the coupling diode unit.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 10, 2005
    Inventors: Byeong-yun Kim, Jung-su Ryu, Bong-jae Kwon
  • Patent number: 5396113
    Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.
    Type: Grant
    Filed: July 31, 1992
    Date of Patent: March 7, 1995
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Yong-Bo Park, Byeong-Yun Kim, Hyung-Kyu Lim
  • Patent number: 5305279
    Abstract: The invention relates to word line selection logic circuits for a semiconductor memory device composed of a plurality of memory blocks. Word line selection logic circuits are composed of groups of word line blocks, and semiconductors for switches operated by an output signal from a block selection decoder to activate a selected word line block. The switches are assigned to each block, and one of the word lines within the memory blocks is selected by supplying the activated word line block with an output signal from a row decoder which ensures improvement in access time and high density.
    Type: Grant
    Filed: March 23, 1992
    Date of Patent: April 19, 1994
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Choul Park, Seong-Jin Han, Byeong-Yun Kim
  • Patent number: 5121356
    Abstract: A write driver of a semiconductor memory device is disclosed which includes: a data input incorporating a noninverted data input portion and an inverted data input portion for buffering an inputted data signal and an inverted data signal in response to write enable signal; a pulse generator generating a first control pulse signal in response to a state transition of the data signal or inverted data signal and a phase-inverted second control pulse signal of the first control pulse signal in response to an inverted write enable signal; a transmitter for transmitting the inverted and noninverted data which have been buffered to a pair of data lines in response to the first control pulse signal; and a precharger for precharging the pair of data lines in response to the second control pulse signal.
    Type: Grant
    Filed: September 6, 1990
    Date of Patent: June 9, 1992
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Yong-bo Park, Byeong-yun Kim
  • Patent number: 5067109
    Abstract: For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three
    Type: Grant
    Filed: August 30, 1988
    Date of Patent: November 19, 1991
    Assignees: Samsung Semiconductor, Telecommunications Co., Ltd.
    Inventors: Byeong-Yun Kim, Tae-Sung Jung, Yong-Bo Park
  • Patent number: 4972373
    Abstract: A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM.
    Type: Grant
    Filed: December 17, 1987
    Date of Patent: November 20, 1990
    Assignee: Samsung Semiconductors & Telecommunications Co., Ltd.
    Inventors: Byeong-Yun Kim, Choong-Keun Kwark, Hee-Choul Park