Patents by Inventor Byeong-Ho Cho

Byeong-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153513
    Abstract: A complex number quantization-based audio signal encoding method may comprise: estimating a scale factor for each subband of an input audio signal; performing complex magnitude scaling for each subband based on the scale factor; and performing polar quantization on a complex frequency coefficient for each subband, wherein the performing the polar quantization for each subband comprises applying two or more different magnitude quantization techniques based on the magnitude of the complex frequency coefficient scaled for each subband.
    Type: Application
    Filed: November 6, 2023
    Publication date: May 9, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Byeong Ho CHO, Seung Kwon BEACK, Jong Mo SUNG, Tae Jin LEE, Woo Taek LIM, In Seon JANG
  • Publication number: 20240151361
    Abstract: A hydrogen supply method includes a two-side heat exchange mode in which both introducing a second fluid into a hydrogen storage part after the second fluid exchanges heat with a first fluid in a second heat exchanger in a state in which a compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in a thermal device are performed. The method also includes a one-side heat exchange mode in which one of introducing the second fluid into the hydrogen storage part after the second fluid exchanges heat with the first fluid in the second heat exchanger in a state in which the compressor is driven to compress the first fluid and introducing the second fluid into the hydrogen storage part after the second fluid is heated or cooled in the thermal device is performed.
    Type: Application
    Filed: August 30, 2023
    Publication date: May 9, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Yeon Ho Kim, Hoon Mo Park, Kyung Moon Lee, Dong Hoon Nam, Ji Hye Park, Young Jin Cho, Jea Wan Kim, Byeong Soo Shin, Ji Hoon Lee, Ho Young Jeong, Suk Hoon Hong, Man Hee Park, Yeong Jun Kim, Jae Yeon Kim, Ho Chan An
  • Publication number: 20240120324
    Abstract: An apparatus for fabricating a display panel, including a film fixing module configured to fix a stretched film on which a plurality of light emitting elements are arranged, a film pressurizing module configured to pressurize the stretched film, a first thickness detection module configured to detect, at each pressurization step, a modulus of elasticity and a change in thickness of the stretched film that is pressurized and stretched by the film pressurizing module, a second thickness detection module configured to detect, at each pressurization step, a change in thickness of an adhesive applied in a front direction of the stretched film, an image detection module configured to photograph the plurality of light emitting elements arranged on the stretched film for each pressurization step and to detect a change in arrangement information of the light emitting elements, and a main processor configured to database feature change information.
    Type: Application
    Filed: September 6, 2023
    Publication date: April 11, 2024
    Inventors: Tae Hee LEE, Kyung Ho KIM, Young Seok SEO, Joo Woan CHO, Byeong Hwa CHO
  • Publication number: 20240120214
    Abstract: An apparatus for fabricating a display panel, the apparatus including: a loading module configured to accommodate a large-area fabricating substrate, the loading module being configured to adjust an inclination of the large-area fabricating substrate from a rear surface of the large-area fabricating substrate and to press the large-area fabricating substrate; and an element transfer module configured to transfer a plurality of light emitting elements or an integrated circuit onto the large-area fabricating substrate and configured to bond and press a wafer on which the plurality of light emitting elements or the at least one integrated circuit is located onto the large-area fabricating substrate.
    Type: Application
    Filed: September 18, 2023
    Publication date: April 11, 2024
    Inventors: Tae Hee LEE, Kyung Ho KIM, Young Seok SEO, Joo Woan CHO, Byeong Hwa CHOI
  • Patent number: 11881227
    Abstract: A method, executed by a processor for compressing an audio signal in multiple layers, may comprise: (a) restoring, in a highest layer, an input audio signal as a first signal; (b) restoring, in at least one intermediate layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in the highest layer or an immediately previous intermediate layer, from the input audio signal as a second signal; and (c) restoring, in a lowest layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in an intermediate layer immediately before the lowest layer, from the input audio signal as a third signal, wherein the first signal, the second signal, and the third signal are combined to output a final restoration audio signal.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: January 23, 2024
    Assignees: ELECTRONICS AND TELECOMMUNICATIONS RESERCH INSTITUTE, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: In Seon Jang, Seung Kwon Beack, Jong Mo Sung, Tae Jin Lee, Woo Taek Lim, Byeong Ho Cho, Hong Goo Kang, Ji Hyun Lee, Chan Woo Lee, Hyung Seob Lim
  • Publication number: 20230298603
    Abstract: A method for encoding an input signal using N flow blocks (N is a natural number greater than or equal to 2) and (N?1) split block(s), which is performed by a processor, may comprise: transmitting, by a k-th flow block (k is a natural number greater than or equal to 1 and less than or equal to N?1) among the N flow blocks, a k-th transformation signal obtained by transforming a received signal into a latent representation to a k-th split block among the (N?1) split block(s); splitting, by the k-th split block, the k-th transformation signal by a predetermined ratio, into a first split signal and a second split signal; transmitting, by the k-th split block, the first split signal to a (k+1)-th flow block; and quantizing a signal transformed by an N-th flow block and the second split signals using a quantization block.
    Type: Application
    Filed: January 4, 2023
    Publication date: September 21, 2023
    Inventors: In Seon JANG, Seung Kwon BEACK, Jong Mo SUNG, Tae Jin LEE, Woo Taek LIM, Byeong Ho CHO
  • Publication number: 20230267940
    Abstract: A method, executed by a processor for compressing an audio signal in multiple layers, may comprise: (a) restoring, in a highest layer, an input audio signal as a first signal; (b) restoring, in at least one intermediate layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in the highest layer or an immediately previous intermediate layer, from the input audio signal as a second signal; and (c) restoring, in a lowest layer, a signal obtained by subtracting an upsampled signal, which is obtained by upsampling the audio signal restored in an intermediate layer immediately before the lowest layer, from the input audio signal as a third signal, wherein the first signal, the second signal, and the third signal are combined to output a final restoration audio signal.
    Type: Application
    Filed: January 13, 2023
    Publication date: August 24, 2023
    Applicants: Electronics and Telecommunications Research Institute, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: In Seon JANG, Seung Kwon BEACK, Jong Mo SUNG, Tae Jin LEE, Woo Taek LIM, Byeong Ho CHO, Hong Goo KANG, Ji Hyun LEE, Chan Woo LEE, Hyung Seob LIM
  • Publication number: 20230267950
    Abstract: A generative adversarial network-based audio signal generation model for generating a high quality audio signal may comprise: a generator generating an audio signal with an external input; a harmonic-percussive separation model separating the generated audio signal into a harmonic component signal and a percussive component signal; and at least one discriminator evaluating whether each of the harmonic component signal and the percussive component signal is real or fake.
    Type: Application
    Filed: January 13, 2023
    Publication date: August 24, 2023
    Applicants: Electronics and Telecommunications Research Institute, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: In Seon JANG, Seung Kwon BEACK, Jong Mo SUNG, Tae Jin LEE, Woo Taek LIM, Byeong Ho CHO, Hong Goo KANG, Ji Hyun LEE, Chan Woo LEE, Hyung Seob LIM
  • Patent number: 8288242
    Abstract: Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: October 16, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Sung Woo Ko
  • Publication number: 20110300713
    Abstract: Methods are disclosed for fabricating an overlay vernier key. A method includes forming a pattern layer and an insulating layer over a semiconductor substrate. The insulating layer is etched to form insulating layer patterns to partially expose the pattern layer. Spacers are formed on sidewalls of the insulating layer patterns. The insulating layer patterns are removed while leaving the spacers to obtain a spacer-shaped etch mask. The pattern layer is etched using the spacer-shaped etch mask to form vernier patterns. At least one of the vernier patterns has a hollow shape.
    Type: Application
    Filed: August 16, 2011
    Publication date: December 8, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventors: Byeong Ho CHO, Sung Woo KO
  • Patent number: 8045139
    Abstract: An exposure apparatus of a semiconductor device may include an exposure light source; an asymmetric adjustment filter for asymmetrically adjusting intensity of a light which passes through the exposure light source; a photomask for passing the light of which intensity is adjusted by the asymmetric adjustment filter; a projection lens for projecting the light passing through the photomask; and a wafer stage for mounting a wafer on which an image is formed by the light from the projection lens.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 25, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Dong Sook Chang
  • Patent number: 7999399
    Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 16, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Sung Woo Ko
  • Publication number: 20090002657
    Abstract: An exposure apparatus of a semiconductor device may include an exposure light source; an asymmetric adjustment filter for asymmetrically adjusting intensity of a light which passes through the exposure light source; a photomask for passing the light of which intensity is adjusted by the asymmetric adjustment filter; a projection lens for projecting the light passing through the photomask; and a wafer stage for mounting a wafer on which an image is formed by the light from the projection lens.
    Type: Application
    Filed: December 13, 2007
    Publication date: January 1, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Byeong Ho Cho, Dong Sook Chang
  • Publication number: 20080003705
    Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.
    Type: Application
    Filed: December 29, 2006
    Publication date: January 3, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Sung Woo Ko
  • Publication number: 20070292776
    Abstract: A substrate includes an overlay vernier key structure that includes an outer pattern formed over one layer over a semiconductor substrate, as a reference for an overlay measurement, and an inner pattern comprising a cluster of vernier patterns formed over another layer.
    Type: Application
    Filed: June 6, 2007
    Publication date: December 20, 2007
    Applicant: Hynix Semiconductor Inc.
    Inventors: Byeong Ho Cho, Yeong Bae Ahn
  • Patent number: 5294695
    Abstract: The present invention relates to a process for preparing a polyethylene naphthalate possessed with high viscosity, characterized by sloving of various problems of the prior art by controlling the rate of the polycondensation reaction.Particularly, the present invention provides a process for preparing polyethylene naphthalate from an esterification reaction product of naphtalene dicarboxylic acid or an alkyl ester thereof and a diol, which comprises polycondensing the esterification reaction product in the presence of a polycondensation catalyst in two steps wherein the first step is carried out at a pressure ranging from 500 to 30 torr and the second step is carried out at a pressure ranging from 10 to 0.1 torr with controlling the reaction rate such that the differential increase of the intrinsic viscosity of the resultant polymer can satisfy the following equations:IV(t.sub.1)-IV(t.sub.0)<0.4 dl/g (1)IV(t.sub.2)-IV(t.sub.0)>0.3 dl/g (2)wherein: IV(t.sub.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: March 15, 1994
    Assignee: SKC Limited
    Inventors: Kwan-Kyung Lee, Byeong-Ho Cho, Yong-Won Kim
  • Patent number: 5288781
    Abstract: The present invention relates to a biaxially oriented polyester film comprising a metallic alkylbenzene sulfonate derivative of formula(I), polyethylene glycol and, optionally, bis(4-.beta.-hydroxyalkoxyphenyl) sulfones of formula(II), which has improved antistatic property, clarity, mechanical properties and heat resistance: ##STR1## wherein: R represents an optionally substituted C.sub.8-25 alkyl group;M represents an alkali or alkali earth metal;m is an integer of 100 or fewer; andn is an integer from 1 to 10.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: February 22, 1994
    Assignee: SKC Limited
    Inventors: Kwang-Jin Song, Byeong-Ho Cho, Yong-Won Kim