Abstract: A memory device configured to receive a processing command from an external host device may be provided. The memory device may comprise an in-memory processor configured to perform an in-memory processing operation in response to the processing command, and an error report circuit configured to provide, in response to the processing command, one or more error records indicating errors detected during the in-memory processing operation, to the external host device in response to the processing command.

Abstract: Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

Abstract: A memory controller includes a plurality of computing units and a controller. The plurality of computing units perform calculations related to a matrix multiplication. The controller identify first information indicating a plurality of vectors required for the calculations with respect to a plurality of rows of a matrix, identify second information indicating at least one row to which each of the plurality of vectors corresponds among the plurality of rows, and control the plurality of computing units to perform the calculations with respect to the plurality of rows by sequentially inputting the plurality of vectors into the plurality of computing units based on the first information and the second information.

Abstract: An in-memory processing memory device may include: a bank including a cell array; and a processing in memory (PIM) block, associated with the bank, including a register that stores a plurality of instructions. The PIM block is configured to: acquire one or more instructions of the plurality of instructions stored in the register; determine whether the one or more instructions operate independently of the bank; and based on the one or more instructions operating independently of the bank, perform computational processing corresponding to the one or more instructions during a first time interval in which the bank is in an inactive state.

Abstract: A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.

Abstract: Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

Abstract: A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Abstract: The present invention is provided with a delay unit for applying a function of a double-pole contact switch and a control function of an activation switch, so as for the contact switch and the activation switch not to operate simultaneously when turned on. Accordingly, when a predetermined time elapses after the double-pole contact switch operates first to prevent an inrush current shock, the activation switch generates a control signal to safely operate an internal circuit such as a central processing device or a control device, so that an electronic product is turned on without an electrical shock or a significant spark. Moreover, if power is cut off by software or the internal circuit is turned off in response to a control signal of the activation switch after an ON button of the electronic product is pressed, the double-pole contact switch is automatically turned off immediately or over a time interval, so that standby power is cut off completely, safely, conveniently, and effectively.

Abstract: The present invention is provided with a delay unit for applying a function of a double-pole contact switch and a control function of an activation switch, so as for the contact switch and the activation switch not to operate simultaneously when turned on. Accordingly, when a predetermined time elapses after the double-pole contact switch operates first to prevent an inrush current shock, the activation switch generates a control signal to safely operate an internal circuit such as a central processing device or a control device, so that an electronic product is turned on without an electrical shock or a significant spark. Moreover, if power is cut off by software or the internal circuit is turned off in response to a control signal of the activation switch after an ON button of the electronic product is pressed, the double-pole contact switch is automatically turned off immediately or over a time interval, so that standby power is cut off completely, safely, conveniently, and effectively.