Abstract: A dual release actuator for a vehicle seat includes a motor, a cable carrier configured to receive power of the motor, thereby rotating to selectively pull one of two different cables, a Hall sensor to sense rotation of the motor, and a controller configured to count a sensing pulse of the Hall sensor for controlling rotation of the motor.

Abstract: A vehicular heat management system includes a refrigerant circulation line configured to generate hot energy or cold energy depending on a flow direction of a refrigerant, a heater core side coolant circulation line configured to transfer refrigerant heat generated in the refrigerant circulation line to a heater core to heat a passenger compartment, and a battery side coolant circulation line configured to receive coolant heat of the heater core side coolant circulation line via a coolant and then circulate the coolant through a battery to preheat the battery.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a line passing through a center of the first coupling member with respect to the second coupling member to be positioned in one of up/down/left/right directions, in a test for setting the layout of the brake hose.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a bend angle between the first coupling member and the second coupling member, in a test for setting the layout of the brake hose.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a line passing through a center of the first coupling member with respect to the second coupling member to be positioned in one of up/down/left/right directions, in a test for setting the layout of the brake hose.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a bend angle between the first coupling member and the second coupling member, in a test for setting the layout of the brake hose.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a line passing through a center of the first coupling member with respect to the second coupling member to be positioned in one of up/down/left/right directions, in a test for setting the layout of the brake hose.

Abstract: In embodiments, a connector for setting a layout of a brake hose includes a first coupling member coupled to one end of the brake hose; a second coupling member disposed to be spaced apart from the first coupling member, and coupled to the caliper housing or the frame of the master cylinder; and an adjusting unit connected at one end thereof to the first coupling member, connected at other end thereof to the second coupling member, and configured to adjust a shortest length between a bottom surface of the first coupling member and an outer circumferential surface of the second coupling member and to adjust a bend angle between the first coupling member and the second coupling member, in a test for setting the layout of the brake hose.

Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.

Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.

Abstract: A semiconductor memory device includes a substrate including a cell region and peripheral region. The cell region is equipped with a photolithographic reference mark pattern and includes a memory cell array region and a staircase-shaped connection region connected to memory cells of the memory cell array region.

Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.

Abstract: A field-effect transistor has at least one electrode disposed independently of source and drain electrodes and in direct contact with the surface of a semiconductor channel to form a schottky barrier, so that it is possible to easily control the schottky barrier.