Abstract: An electronic device is provided. The electronic device includes at least one display, a memory configured to store an application and a database including information on a plurality of controllers, and a processor, wherein the processor is configured to display a content including at least one object in relation to an execution of the application in a first area of the display, determine a controller corresponding to the application based on the database, and output the determined controller to a second area of the display.

Abstract: An electronic device is provided. The electronic device includes at least one display, a memory configured to store an application and a database including information on a plurality of controllers, and a processor, wherein the processor is configured to display a content including at least one object in relation to an execution of the application in a first area of the display, determine a controller corresponding to the application based on the database, and output the determined controller to a second area of the display.

Abstract: The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks. In accordance with this configuration, upon performing a merge operation, hot pages and cold pages are determined, and the hot pages are respectively distributed to empty blocks, so that concentration of an erase operation on a specific physical block may be avoided, thus wear-leveling may be performed more efficiently.

Abstract: The present invention provides a flash memory controller for mapping the logical addresses to the physical addresses of memory including a plurality of blocks, each having a plurality of pages, wherein the memory controller includes a processor. The processor includes hot page decision unit and an address translation unit. The hot page decision unit classifies pages in each block into hot pages and cold pages based on a predetermined criterion. When there is a plurality of the classified hot pages, the address translation unit respectively arranges the classified hot pages in different target blocks. In accordance with this configuration, upon performing a merge operation, hot pages and cold pages are determined, and the hot pages are respectively distributed to empty blocks, so that concentration of an erase operation on a specific physical block may be avoided, thus wear-leveling may be performed more efficiently.