Abstract: A liquid crystal display is provided comprising an LCD panel including data lines formed along a column direction, gate lines formed along a row direction perpendicular to the column direction, and a plurality of pixels arranged in a matrix pattern at intersections of the data lines and the gate lines, a data driver that supplies data voltages to the data lines, and a gate driver that sequentially supplies gate pulses to the gate lines. Subpixels of each of the pixels share one data line through which a data voltage is sequentially charged to the subpixels in a time-division manner. A column-directional length of each of the subpixels is longer than a row-directional length of each of the subpixels.

Abstract: A touch sensor integrated type display device includes: a display panel including: pixels connected to data lines and gate lines and division-driven into a plurality of panel blocks, and a plurality of touch sensors connected to the pixels, a display driving circuit providing data of an input image to the pixels in multiple display periods divided from one frame period, and a touch sensing circuit driving the touch sensors and sensing a touch input in a touch sensing period allocated between the display periods of the frame period, adjacent panel blocks being division-driven in the display periods that are separated from each other with the touch sensing period, in which the touch sensors are driven, interposed therebetween, the display driving circuit including a shift register: shifting a gate pulse in accordance with a shift clock timing, and sequentially supplying the gate pulse to the gate lines.

Abstract: A display device includes: a pixel array including pixels at intersections of data lines and gate lines, a shift register including stages connected as a cascade, the shift register sequentially supplying gate pulses to the gate lines, and a node controller controlling nodes in the shift register, a first stage including: a pull-up transistor charging the output based on a Q node for a first gate pulse, a pull-down transistor discharging the output to a gate-low voltage based on a QB node voltage, a start controller pre-charging the Q node, and a QB node discharge controller discharging the QB node to a first low-potential voltage based on a first reset signal input line (IL), the node controller including a first reset signal generator that, during a vertical blanking interval of each frame, charges the first reset signal IL in response to a turn-on voltage applied to a gate-low voltage IL.

Abstract: A display device and a gate driver circuit of the display device are disclosed. The display device includes a shift register that shifts a gate pulse in accordance with a shift clock and sequentially supplies the gate pulse to gate lines. At least one stage of the shift register includes a discharge blocking node connected to a source terminal of the second transistor, and a discharge blocking circuit configured to charge the discharge blocking node when the Q node is charged, and discharge the discharge blocking node when the Q node is discharged.

Abstract: Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.

Abstract: The present disclosure relates to a touch sensor integrated display device capable of preventing generation of a defective image between touch/common electrodes, which includes a plurality of gate lines and a plurality of data lines intersecting the gate lines, a plurality of pixel electrodes, a plurality of touch/common electrodes and a plurality of touch/common lines. The plurality of pixel electrodes are respectively disposed in regions defined by intersections of the plurality of data lines and the plurality of gate lines and provided with data voltages. The plurality of touch/common electrodes are arranged to generate electric fields with the plurality of pixel electrodes and to correspond to parts of the plurality of pixel electrodes. The plurality of touch/common lines are respectively connected to the plurality of touch/common electrodes. Each touch/common electrode overlap with at least one gate line shared by neighboring touch/common electrodes arranged in a data line arrangement direction.

Abstract: A display device includes a display panel including a display driving circuit, and a touch sensing circuit. The display panel includes first and second panel blocks, each including pixel arrays including touch sensors. The display driving circuit includes a shift register for sequentially outputting a gate pulse applied to a gate line. The shift register includes first and second shift registers and a compensation stage. The first shift register applies a gate pulse to gate lines arranged in the first panel block, and the second shift register applies a gate pulse to gate lines arranged in the second panel block during at least a portion of the display period when a node of the second shift register is charged to a predetermined level. The compensation stage charges the node of the second shift register upon receiving a bridge clock during a touch sensing period of the first panel block.

Abstract: The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Abstract: Provided are a display device, a scan driver, and a method of manufacturing the same. A scan driver includes: a level shifter configured to output a power and a signal, and a scan signal generating circuit configured to generate a scan signal based on the power and the signal supplied from the level shifter, the scan signal generating circuit including a buffer configured to transmit a clock signal to a stage of a shift register, the buffer including two inverters, one of the two inverters being included in a multi-buffer.

Abstract: Disclosed is a display device that may include a display panel, a data driver configured to supply a data signal to the display panel, and a scan driver formed in a non-display area of the display panel, including a shift register composed of a plurality of stages and a level shifter formed outside the display panel, and configured to supply a scan signal to the display panel using the shift register and the level shifter, wherein the shift register is arranged in an output terminal of an N-th stage circuit unit formed in a first non-display area and an output terminal of an N-th compensation circuit unit formed in a second non-display area opposite the first non-display area are paired to be connected to an N-th scan line, wherein the N-th compensation circuit unit outputs a compensation signal to the N-th scan line in response to a node voltage of a neighboring stage circuit unit.

Abstract: The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

Abstract: A liquid crystal display is provided comprising an LCD panel including data lines formed along a column direction, gate lines formed along a row direction perpendicular to the column direction, and a plurality of pixels arranged in a matrix pattern at intersections of the data lines and the gate lines, a data driver that supplies data voltages to the data lines, and a gate driver that sequentially supplies gate pulses to the gate lines. Subpixels of each of the pixels share one data line through which a data voltage is sequentially charged to the subpixels in a time-division manner. A column-directional length of each of the subpixels is longer than a row-directional length of each of the subpixels.