Abstract: In a method for fabricating a surface mountable chip inductor, a spiral coil pattern is formed on a surface of a cylindrical body fabricated by mixing ferrite or ceramic powder with thermoplastic organic binder, the cylindrical body is transformed into a square-shaped body by being inserted into a square-shaped mold and pressure being applied at a certain temperature. An electric characteristic lowering problem can be prevented by forming the coil on the cylindrical body, and transforming the cylindrical body into a square-shaped body to improve surface mounting.

Abstract: In a method for fabricating a surface mountable chip inductor, a spiral coil pattern is formed on a surface of a cylindrical body fabricated by mixing ferrite or ceramic powder with thermoplastic organic binder, the cylindrical body is transformed into a square-shaped body by being inserted into a square-shaped mold and being applied pressure at a certain temperature. An electric characteristic lowering problem can be prevented by forming the coil on the cylindrical body, and transforming the cylindrical body into a square-shaped body is advantageous to surface mounting.

Abstract: An array type multi-chip device and a fabrication method therefor form a plurality of devices of the same kind or different kinds into a single chip. The array type multi-chip device includes: an array type sintered body in which a plurality of unit devices are arranged such that internal electrodes of each of the unit devices are exposed at opposite side surfaces of the array type sintered body; glass pastes formed at portions of the side surfaces of the array type sintered body between the internal electrodes of the adjacent unit devices; external electrodes of conductive paste formed to cover the internal electrodes at the surfaces of the sintered body between the adjacent glass pastes and overlapping the glass pastes; and nickel and solder platings formed on surfaces of the external electrodes.

Abstract: A low capacitance chip varistor and a fabrication method thereof are described, which are capable of protecting the electronic elements of an electronic instrument from an external and internal surge and being well applicable to an electronic element which requires a low capacitance, and the low capacitance chip varistor includes at least one sheet support layer formed of a member having a low dielectric constant, a varistor layer including at least more than one varistor coating layer formed on the support layer, at least more than two internal electrode folded with a predetermined portion of the varistor layer to be connected with the varistor layer, one end of each of which is extended from a lateral surface of the support layer, and a pair of integrally formed external electrodes formed on a lateral surface of a varistor stack member integrally formed of the support layer, the varistor layer and the internal electrodes to be connected with one end portion of each internal electrode.