Abstract: The present invention relates to a high speed line equalizer and a method thereof. The high speed line equalizer receives and amplifies one clock signal and at least more than one data signal. The high speed line equalizer comprises an input buffer, a first filter, at least more than one second filter, and an adaptive loop. The input buffer amplifies the clock signal. The first filter controls a high frequency gain of the clock signal according to a gain control signal. The at least more one second filter controls a high frequency gain of the at least more than one data signal according to the gain control signal. The adaptive loop calculates a gain difference between high frequency components of the amplified clock signal from the input buffer and the clock signal of which high frequency gain is controlled and outputs the gain difference as the gain control signal.

Abstract: The present invention relates to a high speed line equalizer and a method thereof. The high speed line equalizer receives and amplifies one clock signal and at least more than one data signal. The high speed line equalizer comprises an input buffer, a first filter, at least more than one second filter, and an adaptive loop. The input buffer amplifies the clock signal. The first filter controls a high frequency gain of the clock signal according to a gain control signal. The at least more one second filter controls a high frequency gain of the at least more than one data signal according to the gain control signal. The adaptive loop calculates a gain difference between high frequency components of the amplified clock signal from the input buffer and the clock signal of which high frequency gain is controlled and outputs the gain difference as the gain control signal.