Patents by Inventor Byong-hyun JANG
Byong-hyun JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10559584Abstract: A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.Type: GrantFiled: February 7, 2017Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Yeoung Choi, Bio Kim, Young Wan Kim, Jung Ho Kim, Young Seon Son, Jae Young Ahn, Byong Hyun Jang
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Patent number: 10109747Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: GrantFiled: August 20, 2015Date of Patent: October 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byong-Hyun Jang, Juhyung Kim, Woonkyung Lee, Jaegoo Lee, Chaeho Kim, Junkyu Yang, Phil Ouk Nam, Jaeyoung Ahn, Kihyun Hwang
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Patent number: 10103170Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.Type: GrantFiled: October 16, 2017Date of Patent: October 16, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-hyun Jang, Dongchul Yoo, Woojin Jang, Jaeyoung Ahn, Junkyu Yang
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Publication number: 20180114794Abstract: A semiconductor device includes word lines vertically stacked on top of each other on a substrate, insulating patterns between the word lines, a vertical pillar connected to the substrate, and residual sacrificial patterns on the substrate at sides of the word lines. The vertical pillar penetrates the word lines and the insulating patterns. Each of the insulating patterns includes a first portion between the word lines and a second portion extending from the first portion and between the residual sacrificial patterns. A first thickness of the first portion is smaller than a second thickness of the second portion.Type: ApplicationFiled: October 16, 2017Publication date: April 26, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Byong-hyun JANG, Dongchul YOO, Woojin JANG, Jaeyoung AHN, Junkyu YANG
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Publication number: 20180012902Abstract: A semiconductor device including a dielectric layer is provided. The semiconductor device includes a stack structure, and a vertical structure within the stack structure. The vertical structure includes a lower region having a first width and an upper region having a second width, greater than the first width. The vertical structure further includes two dielectric layers of which respective ratios of lower thicknesses in the lower region to upper thicknesses in the upper region are different from each other.Type: ApplicationFiled: February 7, 2017Publication date: January 11, 2018Inventors: Eun Yeoung Choi, Bio Kim, Young Wan Kim, Jung Ho Kim, Young Seon Son, Jae Young Ahn, Byong Hyun Jang
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Patent number: 9653565Abstract: A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.Type: GrantFiled: September 25, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-hyun Jang, Dongchul Yoo, Jaeyoung Ahn, Hunhyeong Lim
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Patent number: 9431414Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.Type: GrantFiled: October 17, 2014Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-Hyun Jang, Dong-Chul Yoo, Ki-Hyun Hwang, Phil-Ouk Nam, Jae-Young Ahn
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Patent number: 9397114Abstract: Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.Type: GrantFiled: May 18, 2012Date of Patent: July 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jumi Yun, Kwangmin Park, Dongchul Yoo, Byong-hyun Jang
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Patent number: 9324730Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: GrantFiled: January 21, 2015Date of Patent: April 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil-Ouk Nam, Dong-Chul Yoo, Bi-O Kim, Jae-Young Ahn, Byong-Hyun Jang, Ki-Hyun Hwang
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Publication number: 20160093634Abstract: A three dimensional semiconductor memory device includes a vertical channel structure extending in a vertical direction on a substrate; interlayer insulating layers surrounding the vertical channel structure and being stacked in the vertical direction on the substrate, gate electrodes surrounding the vertical channel structure and being disposed between the interlayer insulating layers, corners of the gate electrodes adjacent to the vertical channel structure being rounded, and auxiliary gate insulating patterns disposed between the gate electrodes and the vertical channel structure, wherein a side surface of the auxiliary gate insulating pattern is substantially coplanar with a side surface of the interlayer insulating layer in the vertical direction on the substrate.Type: ApplicationFiled: September 25, 2015Publication date: March 31, 2016Inventors: Byong-hyun Jang, Dongchul YOO, Jaeyoung AHN, Hunhyeong LIM
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Publication number: 20150357346Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: BYONG-HYUN JANG, JUHYUNG KIM, WOON KYUNG LEE, JAEGOO LEE, CHAEHO KIM, JUNKYU YANG, PHIL OUK NAM, JAEYOUNG AHN, KlHYUN HWANG
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Patent number: 9130054Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: GrantFiled: March 13, 2013Date of Patent: September 8, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byong-hyun Jang, Juhyung Kim, Woonkyung Lee, Jaegoo Lee, Chaeho Kim, Junkyu Yang, Phil Ouk Nam, Jaeyoung Ahn, Kihyun Hwang
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Publication number: 20150206900Abstract: A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.Type: ApplicationFiled: January 21, 2015Publication date: July 23, 2015Inventors: Phil-Ouk NAM, Dong-Chul YOO, Bi-O KIM, Jae-Young AHN, Byong-Hyun JANG, Ki-Hyun HWANG
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Patent number: 9082659Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: March 10, 2015Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20150187790Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20150145021Abstract: Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.Type: ApplicationFiled: October 17, 2014Publication date: May 28, 2015Inventors: Byong-Hyun Jang, Dong-Chul Yoo, Ki-Hyun Hwang, Phil-Ouk Nam, Jae-Young Ahn
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Patent number: 8987805Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: GrantFiled: August 20, 2013Date of Patent: March 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Patent number: 8697498Abstract: A method of manufacturing a Three Dimensional (3D) semiconductor memory device can be provided by forming at least one trench in a plate stack structure to divide the plate stack structure into a plurality of sub-plate stack structures between forming a plurality of vertical active patterns in the plate stack structure and forming pads of a stepped structure from the plate stack structure.Type: GrantFiled: October 28, 2011Date of Patent: April 15, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-hyun Jang, Dongchul Yoo, Chanjin Park, Hanmei Choi
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Publication number: 20140054676Abstract: A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.Type: ApplicationFiled: August 20, 2013Publication date: February 27, 2014Inventors: Phil-Ouk Nam, Jun-Kyu Yang, Byong-Hyun Jang, Ki-Hyun Hwang, Jae-Young Ahn
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Publication number: 20140035026Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.Type: ApplicationFiled: March 13, 2013Publication date: February 6, 2014Inventors: Byong-hyun Jang, Juhyung Kim, Woonkyung Lee, Jaegoo Lee, Chaeho Kim, Junkyu Yang, Phil Ouk Nam, Jaeyoung Ahn, Kihyun Hwang