Patents by Inventor Byong-Joo Kim
Byong-Joo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11985884Abstract: A display device prevents cracks from spreading to an active area. The display device includes a substrate including an active area and a non-active area having a bending area, a thin-film transistor disposed in the active area, a light-emitting element disposed in the active area and connected to the thin-film transistor, an encapsulation layer disposed on the light-emitting element, a touch sensor disposed on the encapsulation layer, a touch pad disposed in the non-active area, a first routing line connecting the touch sensor to the touch pad via a second routing line in the bending area, and a crack prevention layer disposed on the second routing line in the bending area. Thus, the crack prevention layer is capable of preventing the occurrence of cracks in the bending area BA, thus preventing cracks from spreading to the active area AA.Type: GrantFiled: February 16, 2023Date of Patent: May 14, 2024Assignee: LG Display Co., Ltd.Inventors: Sang-Hyuk Won, Min-Joo Kim, Jae-Won Lee, Sang-Hoon Pak, Byong-Hoo Kim, Ji-Hye Lee, Jae-Man Jang, Sung-Jin Kim, Jae-Hyung Jang
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Patent number: 10679972Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.Type: GrantFiled: November 16, 2018Date of Patent: June 9, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Gil Han, Byong-Joo Kim, Yong-Je Lee, Jae-Heung Lee, Seung-Weon Ha
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Publication number: 20190103381Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.Type: ApplicationFiled: November 16, 2018Publication date: April 4, 2019Inventors: Won-Gil HAN, Byong-Joo KIM, Yong-Je LEE, Jae-Heung LEE, Seung-Weon HA
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Patent number: 10147706Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.Type: GrantFiled: June 15, 2017Date of Patent: December 4, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Gil Han, Byong-Joo Kim, Yong-Je Lee, Jae-Heung Lee, Seung-Weon Ha
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Publication number: 20180114776Abstract: A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.Type: ApplicationFiled: June 15, 2017Publication date: April 26, 2018Inventors: Won-Gil HAN, Byong-Joo KIM, Yong-Je LEE, Jae-Heung LEE, Seung-Weon HA
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Patent number: 9384105Abstract: In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.Type: GrantFiled: February 20, 2014Date of Patent: July 5, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kim, Yean-Sang You, Won-Gil Han, Ho-Am Kim, Byong-Joo Kim, Do-Hoon Lee
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Patent number: 9252123Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: GrantFiled: October 3, 2014Date of Patent: February 2, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Gil Han, Se-Yeoul Park, Ho-Tae Jin, Byong-Joo Kim, Yong-Je Lee, Han-Ki Park
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Publication number: 20150031149Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: ApplicationFiled: October 3, 2014Publication date: January 29, 2015Inventors: Won-Gil HAN, Se-Yeoul PARK, Ho-Tae JIN, Byong-Joo KIM, Yong-Je LEE, Han-Ki PARK
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Publication number: 20140359372Abstract: In a method of detecting faults of operation algorithms in a wire bonding machine, individual bond parameters with respect to each of the operation algorithms of the wire bonding machine can be set based on design data including information with respect to conductive wires connected between semiconductor chips of a semiconductor package. Actual conductive wires of an actual semiconductor package can be formed using the wire bonding machine into which the design data can be inputted. Actual data with respect to actual operation algorithms of the wire bonding machine, which can form the actual conductive wires, can be obtained. The actual data can be compared with the individual bond parameters to detect the faults of the operation algorithms of the wire bonding machine. Thus, forming an abnormal conductive wire by the wire bonding machine can be prevented beforehand.Type: ApplicationFiled: February 20, 2014Publication date: December 4, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Min Kim, Yean-Sang You, Won-Gil Han, Ho-Am Kim, Byong-Joo Kim, Do-Hoon Lee
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Publication number: 20130093080Abstract: A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.Type: ApplicationFiled: September 14, 2012Publication date: April 18, 2013Inventors: Won-Gil HAN, Se-Yeoul Park, Ho-Tae Jin, Byong-Joo Kim, Yong-Je Lee, Han-Ki Park