Abstract: Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test is performed when the semiconductor device is operating under a second CAS latency number that is different from the first CAS latency number. This may be accomplished, for example, by increasing the number of clock cycles in the timing clock signal during a CAS latency-variable interval in situations where the CAS latency is changed after generation of the test pattern.

Abstract: Methods of testing a semiconductor device are provided in which a test pattern is generated for the semiconductor device that is based on the semiconductor device operating under a first CAS latency number. Then, the semiconductor device is tested using this test pattern where, at least part of the test is performed when the semiconductor device is operating under a second CAS latency number that is different from the first CAS latency number. This may be accomplished, for example, by increasing the number of clock cycles in the timing clock signal during a CAS latency-variable interval in situations where the CAS latency is changed after generation of the test pattern.