Patents by Inventor Byoung Do Lee
Byoung Do Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9390997Abstract: The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.Type: GrantFiled: December 23, 2013Date of Patent: July 12, 2016Assignee: SK hynix, Inc.Inventors: Jong Hoon Kim, Jae Hyun Son, Byoung Do Lee, Kuk Jin Chun, Woong Kyu Choi
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Publication number: 20150008588Abstract: The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.Type: ApplicationFiled: December 23, 2013Publication date: January 8, 2015Applicant: SK hynix, Inc.Inventors: Jong Hoon KIM, Jae Hyun SON, Byoung Do LEE, Kuk Jin CHUN, Woong Kyu CHOI
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Patent number: 8810309Abstract: A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.Type: GrantFiled: December 20, 2011Date of Patent: August 19, 2014Assignee: SK Hynix Inc.Inventors: Dae Woong Lee, Yu Gyeong Hwang, Jae Hyun Son, Tae Min Kang, Chul Keun Yoon, Byoung Do Lee, Yu Hwan Kim
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Patent number: 8680688Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.Type: GrantFiled: September 12, 2012Date of Patent: March 25, 2014Assignee: SK Hynix Inc.Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Byoung Do Lee, Yu Hwan Kim
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Publication number: 20130001779Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: SK HYNIX INC.Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Byoung Do LEE, Yu Hwan KIM
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Patent number: 8288873Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.Type: GrantFiled: July 16, 2010Date of Patent: October 16, 2012Assignee: Hynix Semiconductor Inc.Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Byoung Do Lee, Yu Hwan Kim
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Publication number: 20120154020Abstract: A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals.Type: ApplicationFiled: December 20, 2011Publication date: June 21, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Dae Woong LEE, Yu Gyeong HWANG, Jae Hyun SON, Tae Min KANG, Chul Keun YOON, Byoung Do LEE, Yu Hwan KIM
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Patent number: 8164200Abstract: A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.Type: GrantFiled: July 13, 2010Date of Patent: April 24, 2012Assignee: Hynix Semiconductor Inc.Inventors: Tae Min Kang, You Kyung Hwang, Jae-hyun Son, Dae Woong Lee, Chul Keun Yoon, Byoung Do Lee, Yu Hwan Kim
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Publication number: 20110254167Abstract: A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package.Type: ApplicationFiled: July 16, 2010Publication date: October 20, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Byoung Do LEE, Yu Hwan KIM
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Publication number: 20110121454Abstract: A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members.Type: ApplicationFiled: July 13, 2010Publication date: May 26, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Tae Min KANG, You Kyung HWANG, Jae-hyun SON, Dae Woong LEE, Chul Keun YOON, Byoung Do LEE, Yu Hwan KIM