Patents by Inventor Byoung-don Kong

Byoung-don Kong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240030888
    Abstract: There is provided a substrate for a surface acoustic wave device, comprising a 2-dimensional (2D) crystalline hexagonal boron nitride layer, wherein a surface acoustic wave of the surface acoustic wave device is transmitted through the 2D crystalline hexagonal boron nitride layer.
    Type: Application
    Filed: November 17, 2021
    Publication date: January 25, 2024
    Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
    Inventors: Byoung Don KONG, Seok Hyun YOON, Hyeon Su CHO, Seung Ho LEE, Gyeong Min SEO, Chang Ki BAEK
  • Patent number: 11664382
    Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 30, 2023
    Assignee: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION
    Inventors: Chang-Ki Baek, Gayoung Kim, Byoung-Don Kong, Hyangwoo Kim
  • Publication number: 20220028857
    Abstract: A memory device includes at least one semiconductor layer having a double PN junction, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. In addition, a capacitor-less memory device includes at least one semiconductor layer including a double PN junction, a control gate which contacts the semiconductor layer, and an anode and a cathode which simultaneously contact the semiconductor layer, wherein a junction between the semiconductor layer and the anode is a Schottky junction, and a junction between the semiconductor layer and the cathode is an Ohmic junction. Methods of operating the memory device and the capacitor-less memory device are also disclosed.
    Type: Application
    Filed: June 22, 2021
    Publication date: January 27, 2022
    Inventors: Chang-Ki BAEK, Gayoung KIM, Byoung-Don KONG, Hyangwoo KIM
  • Patent number: 10192979
    Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: January 29, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater
  • Publication number: 20170012103
    Abstract: A device having: a substrate having a dielectric surface; a gate electrode; a drain electrode; a source electrode having a conductive contact and a two-dimensional material edge; and a dielectric material between the source and the gate. The source is adjacent to the gate. The drain electrode is not laterally between the edge and the gate electrode, and the distance from the drain electrode to the edge is greater than the distance from the gate electrode to the edge. The edge does not contact any other component of the device. The gate, drain, and source are not in electrical contact with each other. There is a line of sight or electron path from the edge to the drain electrode.
    Type: Application
    Filed: July 11, 2016
    Publication date: January 12, 2017
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Jonathan L. Shaw, John Bradley Boos, Kevin Jensen, James G. Champlain, Bradford B. Pate, Byoung-don Kong, Doewon Park, Joan E. Yater