Patents by Inventor Byoung H. Lee
Byoung H. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120256270Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.Type: ApplicationFiled: June 18, 2012Publication date: October 11, 2012Applicant: International Business Machines CorporationInventors: Byoung H. Lee, Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi, Jong Hoan Sim, Seung-Chul Song, Zhibo Zhang
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Patent number: 8236686Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.Type: GrantFiled: May 30, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Byoung H. Lee, Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi, Jong Hoan Sim, Seung-Chul Song, Zhibo Zhang
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Publication number: 20090294867Abstract: Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.Type: ApplicationFiled: May 30, 2008Publication date: December 3, 2009Inventors: Byoung H. Lee, Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi, Jong Hoan Sim, Seung-Chul Song, Zhibo Zhang
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Publication number: 20080251814Abstract: A hetero-bonded SOI substrate comprises a stack of a semiconductor handle substrate, an isolation insulator layer, a depinning dielectric layer, and a top non-silicon semiconductor layer. The depinning layer abuts both the top non-silicon semiconductor layer and the isolation insulator layer and relaxes Fermi level pinning in the top non-silicon semiconductor layer. The top non-silicon semiconductor layer may be a III-V compound semiconductor layer such as GaAs and the depinning dielectric layer may be a (GdxGa1-x)2O3 layer. The interface defect density may be reduced below 5.0×1011 cm?2 eV?1.Type: ApplicationFiled: April 16, 2007Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Byoung H. Lee
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Patent number: 6891228Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: GrantFiled: September 28, 2004Date of Patent: May 10, 2005Assignee: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Patent number: 6828630Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: GrantFiled: January 7, 2003Date of Patent: December 7, 2004Assignee: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Publication number: 20040129979Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.Type: ApplicationFiled: January 7, 2003Publication date: July 8, 2004Applicant: International Business Machines CorporationInventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
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Patent number: 6746924Abstract: A method of forming an asymmetric extension MOSFET using a drain side spacer which allows a choice of source and drain sides for each individual MOSFET device and also allows an independent design or tuning of the source and drain extension implant dose as well as its spacing from the gate. A photoresist mask is formed over at least a portion of each drain region, followed by an angled ion implant during which the photoresist mask and the gate conductor shield the nitride layer over at least a portion of the drain region and at least one sidewall of the gate conductor from damage by the angled ion implant which selectively damages portions of the nitride layer unprotected by the photoresist mask and the gate conductor.Type: GrantFiled: February 27, 2003Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Byoung H. Lee, Anda C. Mocuta
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Patent number: 6653698Abstract: A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.Type: GrantFiled: December 20, 2001Date of Patent: November 25, 2003Assignee: International Business Machines CorporationInventors: Byoung H. Lee, Effendi Leobandung, Ghavam G. Shahidi
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Publication number: 20030119292Abstract: A dual work function CMOS metal gate device provides a composite metal gate electrode structure. The composite metal gate structure includes a bulk metal and a thin metal layer having an appropriate work function for the transistor type and desired threshold voltage, VT. Both N-channel and P-channel transistors are formed to have distinct threshold voltages by incorporating the metal material having the appropriate work function for the desired VT into the composite metal gate electrode. The two different electrodes of the N-channel and P-channel transistors are electrically connected by means of the bulk metal.Type: ApplicationFiled: December 20, 2001Publication date: June 26, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byoung H. Lee, Effendi Leobandung, Ghavam G. Shahidi