Abstract: Provided is a control device connected to a display panel including a controller configured to display images by driving the display panel according to data corresponding to image frames, and a memory connected to the controller. The controller is configured to select at least one of the image frames as a reference image frame, and update stress data corresponding to a partial area of the display panel in the memory based on one image data block selected from image data blocks of the reference image frame.

Abstract: A display device includes pixels connected to scan lines and data lines, each pixel including a driving transistor and at least one light emitting element, and a timing controller configured to generate output data using external input data. The timing controller includes a first compensator configured generate first data by correcting the external input data using at least one of optical measurement information, a threshold voltage of each of the driving transistors, mobility information, dimming information, and temperature information, and an afterimage compensator configured to generate second data based on age information of each light emitting element and the first data, generate third data based on a current amount corresponding to the first data and a current amount corresponding to the second data, and generate the age information by accumulating the third data.

Abstract: A semiconductor device is provided. The semiconductor device comprising a multi-channel active pattern on a substrate, a high dielectric constant insulating layer formed along the multi-channel active pattern on the multi-channel active pattern, wherein the high dielectric constant insulating layer comprises a metal, a silicon nitride layer formed along the high dielectric constant insulating layer on the high dielectric constant insulating layer and a gate electrode on the silicon nitride layer.

Abstract: One aspect of the present disclosure is a pharmaceutical composition which includes (R)—N-[1-(3,5-difluoro-4-methansulfonylamino-phenyl)-ethyl]-3-(2-propyl-6-trifluoromethyl-pyridin-3-yl)-acrylamide as a first component and a cellulosic polymer as a second component, wherein the composition of one aspect of the present disclosure has a formulation characteristic in which crystal formation is delayed for a long time.

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

Abstract: A three-dimensional semiconductor device includes: a source structure including a cell region and an extension region; a gate stacking structure disposed on the source structure, the gate stacking structure including insulating patterns and conductive patterns, which are alternately stacked on each other; an insulating structure disposed on the gate stacking structure, the insulating structure including a plurality of insulating layers; a memory channel structure penetrating the gate stacking structure and electrically connected to the cell region; a separation structure penetrating the gate stacking structure and extending from the cell region to the extension region; and a penetration plug penetrating the gate stacking structure and the extension region, wherein the penetration plug includes: a first plug portion penetrating the gate stacking structure; and a second plug portion on the first plug portion, wherein the separation structure includes: a first separation portion penetrating the gate stacking str

Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.

Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.

Abstract: A lithography apparatus is provided. The apparatus includes: a stage, a first light source unit, an optical system, an image obtaining means, an image edit means, an LC panel, and a second light source unit. The LC panel is coupled with the optical system and receives a signal of the image edited by the image edit means and displays the received image to perform a photo mask function. The second light source unit provides light used in performing an exposure on the test material using the imaged displayed on the LC panel for a photo mask.

Abstract: A memory device may include a switching device and a storage node coupled with the switching device. The storage node may include a first electrode, a second electrode, a data storage layer and at least one contact layer. The data storage layer may be disposed between the first electrode and the second electrode and may include a transition metal oxide or aluminum oxide. The at least one contact layer may be disposed at least one of above or below the data storage layer and may include a conductive metal oxide.

Abstract: Example embodiments relate to a method of fabricating a memory device and a memory device. The method of fabricating a memory device comprises forming a lower electrode and an oxide layer on a lower structure and radiating an energy beam on a region of the oxide layer. The memory device comprises a lower structure and an oxide layer and a lower structure formed on the lower structure, the oxide layer including an electron beam radiation region that received radiation from an electron beam source creating an artificially formed current path through the oxide layer to the lower electrode. A reset current of the memory device may be decreased and stabilized.