Abstract: A liquid crystal display device having first and second substrates; a gate line on the first substrate; a data line crossing the gate line to define a pixel area, the gate line and the data line having a gate insulating film there between; a thin film transistor including a gate electrode, a source electrode, a drain electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode; a common line in parallel to the gate line on the first substrate; a common electrode extended from the common line in the pixel area; and a pixel electrode spaced apart from the common line and the common electrode in the pixel area to be defined in a pixel hole passing through the gate insulating film, wherein the semiconductor layer overlaps with a source and drain metal pattern including the data line, the source electrode and the drain electrode, and wherein the drain electrode protrudes from the semiconductor layer toward an upper portion of the pixel electrode to be connected to

Abstract: A TFT array substrate is fabricated in a reduced number of processes. The TFT array substrate includes gate and data pads with enlarged contact areas to facilitate contact with an inspecting pin of an inspection device. An LCD incorporating the TFT array substrate is inspected by contacting the inspecting pin to the gate and data pads. The TFT array substrate includes first, second, and third conductive pattern groups. The first conductive pattern group includes a gate electrode, a gate line, and a lower gate pad electrode. The second conductive pattern group includes source and drain electrodes, a data line, and a lower data pad electrode. The third conductive pattern group includes a pixel electrode, and upper gate and data pad electrodes. A semiconductor pattern is along and beneath the second conductive pattern group. Gate insulating and protective film patterns are at areas not occupied by the third conductive pattern group.

Abstract: A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.