Abstract: A method of manufacturing a semiconductor device comprising forming a plurality of trench gate electrodes in a semiconductor substrate which protrude from the semiconductor substrate by a predetermined height; forming a polycrystal silicon film on the surface of the substrate; performing an anisotropic etching process on the polycrystal silicon film so as to expose the upper surfaces of the trench gate electrodes and to form spacers on each side of the trench gate electrodes; forming an insulating film on the substrate; forming a plurality of first photoresist patterns; etching the insulating film using the first photoresist patterns in order to form a plurality of insulating film patterns with spaces being formed between the plurality of insulating film patterns; and forming metal film patterns in the spaces between the insulating film patterns in order to form a series of contacts which correspond to the trench gate electrodes.

Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.

Abstract: A method for fabricating a resistive load static random access memory (SRAM) capable of providing a high resistive load without local resistance variation, includes a step of forming an isolated layer on a semiconductor substrate having driver and access transistors provided thereto, a step of selectively etching said isolated layer to provide a butting contact region, a step of forming a doped polysilicon layer on a resulting structure, a step of selectively counter-doping said doped polysilicon layer, and a step of patterning said doped polysilicon layer to provide a power supply line, a butting contact and a high load resistor.

Abstract: A method for manufacturing a trench isolation in a semiconductor device, wherein the method includes the steps of: forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization, thereby forming the trench isolation.

Abstract: A method for manufacturing a trench isolation in a semiconductor device, wherein the method includes the steps of: forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization, thereby forming the trench isolation.