Patents by Inventor Byoung-jun Min

Byoung-jun Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136674
    Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.
    Type: Application
    Filed: January 19, 2022
    Publication date: April 25, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Jong-Sik PARK, Jae-Won LIM, Yu-Sung CHOE, Hak-Kyun KIM, Je-Jun LEE, Byoung-Gu LEE, Duk-Hyun RYU, Kwan-Hee LEE, Jae-Eun LEE, Pil-Kyu PARK, Kwang-Su HWANGBO, Do-Gyun KIM, Geon-Woo MIN, Hae-Jin LIM, Min-Ki JO, Su-Ji CHOI, Bo-Hyun KANG, Jae-Woong KIM, Ji-Min JUNG, Jin-Hak KONG, Soon-O LEE, Kyu-Hyun CHOI
  • Publication number: 20240128517
    Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.
    Type: Application
    Filed: January 19, 2022
    Publication date: April 18, 2024
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Hae-Jin LIM, Jin-Hak KONG, Soon-O LEE, Kyu-Hyun CHOI, Do-Gyun KIM, Su-Ji CHOI, Kwang-Su HWANGBO, Geon-Woo MIN, Min-Ki JO, Jae-Won LIM, Hak-Kyun KIM, Je-Jun LEE, Ji-Min JUNG, Jae-Woong KIM, Jong-Sik PARK, Yu-Sung CHOE, Byoung-Gu LEE, Duk-Hyun RYU, Kwan-Hee LEE, Jae-Eun LEE, Bo-Hyun KANG, Pil-Kyu PARK
  • Patent number: 10120016
    Abstract: A semiconductor test apparatus includes: a tray housing unit configured to house a customer tray loading untested semiconductor chips, secondary semiconductor chips, and non-defective semiconductor chips; a loader configured to locate the untested semiconductor chips supplied from the tray housing unit on a loading set plate and load the untested semiconductor chips onto a test tray; a tester configured to test semiconductor chips loaded on the test tray; an unloader configured to unload semiconductor chips loaded on the test tray, classify the tested semiconductor chips, and locate the classified semiconductor chips on an unloading set plate; and a retest controller configured to transfer the secondary defective semiconductor chips and the non-defective semiconductor chips to the tray housing unit and transfer the first defective semiconductor chips to the loading set plate.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: November 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-young Lee, Byoung-jun Min, Jong-cheol Lee
  • Publication number: 20170102427
    Abstract: A semiconductor test apparatus includes: a tray housing unit configured to house a customer tray loading untested semiconductor chips, secondary semiconductor chips, and non-defective semiconductor chips; a loader configured to locate the untested semiconductor chips supplied from the tray housing unit on a loading set plate and load the untested semiconductor chips onto a test tray; a tester configured to test semiconductor chips loaded on the test tray; an unloader configured to unload semiconductor chips loaded on the test tray, classify the tested semiconductor chips, and locate the classified semiconductor chips on an unloading set plate; and a retest controller configured to transfer the secondary defective semiconductor chips and the non-defective semiconductor chips to the tray housing unit and transfer the first defective semiconductor chips to the loading set plate.
    Type: Application
    Filed: October 5, 2016
    Publication date: April 13, 2017
    Inventors: Dong-young LEE, Byoung-jun MIN, Jong-cheol LEE
  • Publication number: 20160061884
    Abstract: A contact structure for a test handler for electrically testing a semiconductor device, comprising: a base body configured to be driven by a driving unit; at least one first pusher assembly arranged on the base body and configured to push and cool the semiconductor device; and at least one second pusher assembly arranged on the base body and configured to push and heating the semiconductor device.
    Type: Application
    Filed: June 30, 2015
    Publication date: March 3, 2016
    Inventors: Jung-Hyun CHO, Byoung-Jun MIN, Joong-Kyeon PARK
  • Patent number: 8564317
    Abstract: A test socket is provided that includes a socket body to receive an object to be tested, a lid disposed on the socket body, one or more pushers coupled to a first surface of lid to apply force to a first surface of the object toward the socket body, and a temperature controlling member to provide a temperature to the object. A semiconductor package may be tested in a test apparatus that includes the test socket, the methods of testing including receiving a semiconductor package in a socket in a test chamber, applying a first temperature to the test chamber to test the semiconductor package at a first test temperature, and applying a second temperature to the semiconductor package to test the semiconductor package at a second test temperature by controlling the application of the second temperature with the socket.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: October 22, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Jong-Won Han, Seok Goh, Byoung-Jun Min, Jung-Hyeon Kim, Sang-Sik Lee, Bo-Woo Kim, Ho-Jeong Choi
  • Patent number: 7017428
    Abstract: A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: March 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-jun Min, Jeong-ho Bang, Hyun-seop Shim, Hyo-geun Chae
  • Publication number: 20040145387
    Abstract: A method for testing a multi-chip package formed of different types of semiconductor devices, using an integrated burn-in test program which can reduce throughput time, reduce the possibility of error by an operator, and reduce workload. A multi-chip package is tested in burn-in equipment capable of applying a plurality of scan control clock signals. An integrated burn-in test program requires fewer burn-in test programs to be uploaded, fewer contact tests, and fewer bin sorting operations.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 29, 2004
    Inventors: Geum-Jin Yun, Jin-Sung Jung, Seong-Goo Kang, Jeong-Ho Bang, Byoung-Jun Min
  • Publication number: 20040112142
    Abstract: A test kit for a semiconductor package and a method for testing the semiconductor package using the same are provided. The test kit for a semiconductor package includes a pick-and-place tool for picking up and loading/unloading the semiconductor package, a head assembly having a package guider and a socket guider, and a socket which is positioned under the head assembly. The socket guider performs a pre-alignment function for a correct operation of the package guider, before the package guider starts operating. The package guider aligns the semiconductor package.
    Type: Application
    Filed: December 4, 2003
    Publication date: June 17, 2004
    Inventors: Byoung-Jun Min, Jeong-Ho Bang, Hyun-Seop Shim, Hyo-Geun Chae
  • Patent number: 6462534
    Abstract: A loader of semiconductor package burn-in test equipment allows a test socket to be commonly used for semiconductor packages of all sizes. The loader includes a vacuum suction head for picking semiconductor packages to be tested, and a package guider for ensuring that semiconductor packages of any size will be aligned with the test socket. As the semiconductor package is positioned over the test socket by the vacuum suction head of the loader, guide surfaces of the package guider are brought inwardly into guide positions at which the surfaces extend just beneath the vacuum suction head. Any semiconductor package that is not in alignment with the test socket while being held by the vacuum suction head is guided by the guides surfaces into alignment once the vacuum suction is turned off and the package falls from the vacuum suction head. Thus, the package guider serves as an adaptor, eliminating the need for several test sockets having respective adaptors for different sizes of semiconductor packages.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 8, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-goo Kang, Byoung-jun Min, Hyo-geun Chae, Jeong-ho Bang
  • Patent number: 6450839
    Abstract: An embodiment of the present invention provides a circuit board and a socket having mechanical connector for easily connecting and disconnecting a semiconductor integrated circuit device to and from the circuit board. Another embodiment further includes a sub-circuit board for electrically connecting the socket to the circuit board. The socket includes a socket body and a number of socket leads. The socket leads are shaped to compress elastically when inserted in a hole and thereby make contact between the socket leads and inner walls of the holes of the circuit board. The sub-circuit board has connection leads, which make contacts with the through holes of the circuit board in the same manner as the socket leads of the present invention.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: September 17, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung Jun Min, Hyo Geun Chae, Sang Young Choi
  • Publication number: 20020037672
    Abstract: An embodiment of the present invention provides a circuit board and a socket having mechanical connector for easily connecting and disconnecting a semiconductor integrated circuit device to and from the circuit board. Another embodiment further includes a sub-circuit board for electrically connecting the socket to the circuit board. The socket includes a socket body and a number of socket leads. The socket leads are shaped to compress elastically when inserted in a hole and thereby make contact between the socket leads and inner walls of the holes of the circuit board. The sub-circuit board has connection leads, which make contacts with the through holes of the circuit board in the same manner as the socket leads of the present invention.
    Type: Application
    Filed: September 23, 1998
    Publication date: March 28, 2002
    Inventors: BYOUNG JUN MIN, HYO GEUN CHAE, SANG YOUNG CHOI
  • Publication number: 20010026152
    Abstract: A loader of semiconductor package burn-in test equipment allows a test socket to be commonly used for semiconductor packages of all sizes. The loader includes a vacuum suction head for picking semiconductor packages to be tested, and a package guider for ensuring that semiconductor packages of any size will be aligned with the test socket. As the semiconductor package is positioned over the test socket by the vacuum suction head of the loader, guide surfaces of the package guider are brought inwardly into guide positions at which the surfaces extend just beneath the vacuum suction head. Any semiconductor package that is not in alignment with the test socket while being held by the vacuum suction head is guided by the guides surfaces into alignment once the vacuum suction is turned off and the package falls from the vacuum suction head. Thus, the package guider serves as an adaptor, eliminating the need for several test sockets having respective adaptors for different sizes of semiconductor packages.
    Type: Application
    Filed: March 14, 2001
    Publication date: October 4, 2001
    Inventors: Seong-goo Kang, Byoung-jun Min, Hyo-geun Chae, Jeong-ho Bang