Patents by Inventor Byoung Kwan Jeong
Byoung Kwan Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10970002Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a power application timer configured to measure each of plural final power application times, each final power application time being a period of time during which power is applied to the memory controller until the memory controller is turned off after being turned on, and a command blocker configured to disable a set command, among commands that are input from a host to the memory controller depending on a cumulative power application time obtained by accumulating the plural final power application times.Type: GrantFiled: July 22, 2019Date of Patent: April 6, 2021Assignee: SK hynix Inc.Inventors: Tae Kyu Ryu, Young Kyun Shin, Byoung Kwan Jeong
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Publication number: 20200159453Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller may include a power application timer configured to measure each of plural final power application times, each final power application time being a period of time during which power is applied to the memory controller until the memory controller is turned off after being turned on, and a command blocker configured to disable a set command, among commands that are input from a host to the memory controller depending on a cumulative power application time obtained by accumulating the plural final power application times.Type: ApplicationFiled: July 22, 2019Publication date: May 21, 2020Inventors: Tae Kyu RYU, Young Kyun SHIN, Byoung Kwan JEONG
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Publication number: 20180299935Abstract: A memory device may include a memory region, and a control unit for performing an internal operation on the memory region in response to a command received from an external device, and in a wait state in connection with the performance of the internal operation, which depends on the internal operation.Type: ApplicationFiled: November 29, 2017Publication date: October 18, 2018Applicant: SK hynix Inc.Inventors: Byoung Kwan JEONG, Beom Ju SHIN, Keun Hyung KIM
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Publication number: 20150270003Abstract: A method for programming a non-volatile memory includes applying a first program pulse to a program cell one or more times until a threshold voltage of the program cell reaches a preliminary target voltage, which is lower than a target voltage, while supplying a first voltage to a bit line corresponding to the program cell, and applying a second program pulse to the program cell a predetermined number of times while supplying a second voltage, which is higher to than the first voltage, to the bit line after the threshold voltage of the program cell reaches the preliminary target voltage.Type: ApplicationFiled: August 22, 2014Publication date: September 24, 2015Inventors: Byoung-Kwan JEONG, Seong-Je PARK
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Publication number: 20140063980Abstract: An operation method of a semiconductor memory device includes forming a first data distribution by performing a first programming operation during a first write operation, outputting a predetermined data by detecting the first data distribution on the basis of a first reference voltage corresponding to the first programming operation during a first read operation, forming a second data distribution by performing a second programming operation during a second write operation, and outputting data that is the same as the predetermined data corresponding to the first data distribution during the first read operation by detecting the second data distribution on the basis of a second reference voltage corresponding to the second programming operation during a second read operation.Type: ApplicationFiled: December 19, 2012Publication date: March 6, 2014Applicant: SK HYNIX INC.Inventors: Byoung-Kwan JEONG, Jee-Yul KIM
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Patent number: 8630123Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.Type: GrantFiled: January 25, 2013Date of Patent: January 14, 2014Assignee: SK Hynix Inc.Inventors: Byoung Kwan Jeong, Chul Woo Yang
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Patent number: 8514633Abstract: A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value.Type: GrantFiled: December 30, 2010Date of Patent: August 20, 2013Assignee: Hynix Semiconductor Inc.Inventor: Byoung Kwan Jeong
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Patent number: 8374036Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.Type: GrantFiled: November 16, 2009Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventors: Byoung Kwan Jeong, Chul Woo Yang
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Publication number: 20120008413Abstract: A method for operating a semiconductor memory device includes the steps of: erasing memory cells of a memory block to set the memory cells in a first erased state, programming a part of the memory cells of the memory block to convert them into a programmed state, raising threshold voltages of selected memory cells of the memory block and converting the selected memory cells from the programmed state to a second erased state, and reading data from the memory cells in the first erased state, the programmed state, and the second erased state, and outputting the data read from the memory cells in the first and second erased states with the same value.Type: ApplicationFiled: December 30, 2010Publication date: January 12, 2012Inventor: Byoung Kwan JEONG
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Patent number: 8059460Abstract: A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.Type: GrantFiled: December 31, 2009Date of Patent: November 15, 2011Assignee: Hynix Semiconductor Inc.Inventors: Byoung Kwan Jeong, Chul Woo Yang, Mi Sun Yoon
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Publication number: 20100306582Abstract: A method of operating a nonvolatile memory device includes performing a program operation on memory cells included in a selected page, checking whether a verification operation for the programmed memory cells is passed or failed by performing the verification operation, counting a number of error bits for the selected page, if the verification operation is failed, performing an error checking and correction (ECC) algorithm using an error correction circuit, if the counted number of error bits is less than or equal to a number of correctable bits, and storing the counted number of error bits in a specific one of a plurality of memory blocks.Type: ApplicationFiled: May 13, 2010Publication date: December 2, 2010Inventors: Jung Chul Han, Byoung Kwan Jeong
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Publication number: 20100195401Abstract: A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.Type: ApplicationFiled: December 31, 2009Publication date: August 5, 2010Inventors: Byoung Kwan JEONG, Chul Woo Yang, Mi Sun Yoon
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Publication number: 20100124122Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.Type: ApplicationFiled: November 16, 2009Publication date: May 20, 2010Inventors: Byoung Kwan JEONG, Chul Woo Yang
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Patent number: 7684254Abstract: A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.Type: GrantFiled: December 28, 2006Date of Patent: March 23, 2010Assignee: Hynix Semiconductor Inc.Inventors: Min Joong Jung, Byoung Kwan Jeong, Tai Kyu Kang
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Publication number: 20090285351Abstract: The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.Type: ApplicationFiled: June 27, 2008Publication date: November 19, 2009Applicant: Hynix Semiconductor Inc.Inventors: Sang Oh LIM, Byoung Kwan JEONG, Mi Sun YOON
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Patent number: 7609800Abstract: The present invention relates to a unit counter block. According to an aspect of the present invention, the unit counter block includes a D-flipflop, a second MUX, and a first MUX. The-flipflop outputs first and second output signals in synchronism with a clock signal. The second MUX selects any one of external data and the second output signal of the D-flipflop in response to a data load signal and outputs a selected signal. The first MUX transfers any one of the first output signal of the D-flipflop and the output signal of the second MUX as an input signal of the D-flipflop in response to a counter enable signal or the data load signal.Type: GrantFiled: June 27, 2008Date of Patent: October 27, 2009Assignee: Hynix Semiconductor Inc.Inventors: Sang Oh Lim, Byoung Kwan Jeong, Mi Sun Yoon
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Publication number: 20080084766Abstract: A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.Type: ApplicationFiled: December 28, 2006Publication date: April 10, 2008Applicant: Hynix Semiconductor Inc.Inventors: Min Joong Jung, Byoung Kwan Jeong, Tai Kyu Kang