Abstract: A semiconductor device includes a substrate with a conductive pattern. A semiconductor die is electrically connected to the substrate and both the semiconductor die and the substrate are at least partially covered by a package body. In some examples, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In some examples, through-mold vias are included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. In some examples, an interposer is electrically connected to the through-mold vias and may be covered by the package body and/or disposed in spaced relation thereto. In some examples, the interposer may not be electrically connected to the through-mold vias but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a base semiconductor chip, a chip structure on the base semiconductor chip, a connection terminal between the base semiconductor chip and the chip structure, and a molding layer surrounding the chip structure and the connection terminal. The chip structure includes a first semiconductor chip including a first frontside pad and a first backside pad, and a second semiconductor including a second frontside pad and a second backside pad. A lateral surface of the first semiconductor chip is aligned with that of the second semiconductor chip. The first backside pad and the second frontside pad partially overlap each other when viewed in plan while being in direct contact with each other. The first backside pad and the second frontside pad include the same metal and are formed into a single unitary piece.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on a top surface of the first semiconductor chip. The first semiconductor chip includes a conductive pattern disposed on the top surface of the first semiconductor chip and a first protective layer covering the top surface of the first semiconductor chip and at least partially surrounds the conductive pattern. The second semiconductor chip includes a first pad that contacts a first through electrode on a bottom surface of the second semiconductor chip. A second protective layer surrounds the first pad and covers the bottom surface of the second semiconductor chip. A third protection layer fills a first recess defined in the second protective layer to face the inside of the second protective layer. The first protective layer and the third protective layer contact each other.

Abstract: There is provided a camera module including a plurality of ball bearings to support the driving of a lens barrel at the time of compensating for unintended camera movement due to disturbance such as hand shake. The lens barrel may be driven in first and second directions, independently, by one driving force exerted in the first direction perpendicular to an optical axis and by another driving force exerted in the second direction perpendicular to both the optical axis and the first direction, thereby preventing driving displacement from being generated at the time of compensating for unwanted motion such as hand shake while securing reliability against external impact, and having reduced power consumption at the time of compensating for the disturbance.

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

Abstract: An RF catheter for treating hypertrophic cardiomyopathy includes: a body part constituting a catheter body made of a flexible and soft material; and an intraseptal insertion part provided at a distal part of the body part and having one or more electrodes, a tapered tip gradually becoming thinner toward an end thereof, and a guidewire lumen therein, into which a guidewire is inserted, so that during hypertrophic cardiomyopathy treatment, the intraseptal insertion part is inserted into the interventricular septum along the guidewire. A method of treating hypertrophic cardiomyopathy by using an RF ablation catheter includes: i) positioning the guidewire to a hypertrophied septum through a coronary sinus and a septal vein; ii) transferring the RF ablation catheter to the hypertrophied septum; and iii) performing RF ablation by applying RF energy to the electrodes provided at an end part of the RF ablation catheter by using an RF generator.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.

Abstract: A semiconductor package includes a substrate; a substrate pad on the substrate; a first semiconductor chip and a second semiconductor chip on the substrate; a connective terminal between the substrate pad and the first semiconductor chip and between the substrate pad and the second semiconductor chip; a dummy pad on the substrate, and spaced apart from the substrate pad, wherein the dummy pad is between the first semiconductor chip and the second semiconductor chip; and an underfill material layer interposed between the substrate and the first semiconductor chip and between the substrate and the second semiconductor chip, wherein the dummy pad and the substrate pad include a same material.

Abstract: Systems, methods and computer program products for creating 3D representations of bodies are disclosed. The systems, methods and computer program products include the construction of FE meshes representing complex geometries. The complex geometries may be artificially or naturally formed or designed geometries. The techniques reduce the number of elements as much as possible to save on computer run time while maintaining computational accuracy.

Abstract: Provided are an air purifier and an air conditioner including the same. The air purifier includes a ground electrode part, a discharge electrode, at least a pair of magnetic force generators, and a voltage generator. The ground electrode part has at least a pair of flat plates. The discharge electrode is located between the flat plates and separated from the flat plates. The at least a pair of magnetic force generators is provided to the flat plates, respectively, to generate a magnetic field and allow attractive force to be applied between the flat plates. The voltage generator applies a voltage between the ground electrode part and the discharge electrode.

Abstract: Provided is a high-performance n-type Schottky barrier tunneling transistor with low Schottky barrier for electrons due to a Schottky junction formed on a Si (111) surface created through anisotropic etching. The Schottky barrier tunneling transistor includes: a silicon on insulator (SOI) substrate; a source and a drain formed on the SOI substrate; a channel formed between the source and the drain; a gate insulating layer and a gate electrode sequentially formed on the channel; and a sidewall insulating layer formed on both sidewalls of the gate insulating layer and the gate electrode, wherein an interface between the source/drain and the channel is on a Si (111) in the channel, and the source and drain consists of metal silicide through silicidation with a predetermined metal and forms a Schottky junction with the silicon channel.

Abstract: An indoor unit of an air conditioner is provided. The indoor unit has an improved airflow structure, for a rapid air conditioning of the room, a user's convenience, and an efficiency of the air conditioner.

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract: A lithography apparatus is provided. The apparatus includes: a stage, a first light source unit, an optical system, an image obtaining means, an image edit means, an LC panel, and a second light source unit. The LC panel is coupled with the optical system and receives a signal of the image edited by the image edit means and displays the received image to perform a photo mask function. The second light source unit provides light used in performing an exposure on the test material using the imaged displayed on the LC panel for a photo mask.

Abstract: Disclosed is a 3-grid neutral beam source used for etching a semiconductor device. The 3-grid neutral beam source includes a plasma generating chamber, a grid assembly including first to third grids, which are sequentially overlapped with each other by interposing an insulation material therebetween for obtaining a great amount of ion flux at a low ion energy, and a reflective member for converting an ion beam into a neutral beam by reflecting the ion beam. The semiconductor device is prevented from being damaged due to reduced kinetic energy of ions, and an etch rate of the semiconductor device is improved.

Abstract: A pair of training chopsticks for developing intellectual faculties is described. The training chopsticks comprise a first stick, a second stick and a coupling means. The first stick has a thumb-inserting hole for inserting the thumb and a first pad for picking up solids. The thumb-inserting hole is formed on the upper side of the first stick and the first pad is formed on the lower end of the first stick. The second stick has a holding unit for inserting the forefinger and the second finger, an adjusting means for adjusting the fixing position of the holding unit and a second pad for picking up solids. The holding unit has a forefinger-inserting hole for inserting the forefinger and a second finger-inserting hole for inserting the second finger. The coupling means formed on the upper sides of the first and second stick couples the first and second stick at an interval.

Abstract: A backlight system for use in display devices including liquid crystal displays, or in advertising means or in lighting devices includes one or more light sources, a light-glide panel, a light reflecting film, an anisotropic light diffusing film, and a light collimating film. A light source is positioned at one or more edges of the light-guide panel in a predetermined direction. A light reflecting film is placed below the light-guide panel. An anisotropic light diffusing film is placed over the light-guide panel. The anisotropic light diffusing film has directionally different diffusing properties. The light collimating film has a top surface and a smooth bottom surface. The top surface of the light collimating film includes a lenticular layer extending in a predetermined direction. The lenticular layer has a plurality of linear prisms. A reflective polarizer can be employed over the light collimating film.