Abstract: A method of manufacturing a semiconductor device capable of improving a margin of a fabrication process of the semiconductor device, suppressing defect occurrence, and reducing a minimum design rule of a fine pattern is provided. The method of manufacturing a semiconductor device includes forming an input/output (I/O) pad and a metal interconnection, each of the I/O pad and the interconnection including a plurality of line patterns, the plurality of line patterns having the same line widths as each other and being separated by the same distance.

Abstract: A method for detecting failure of database patterns of a photo mask including designing the database patterns of the photo mask according to a design rule of a semiconductor element; performing optical proximity correction (OPC) of the designed database patterns; and detecting failure of the database patterns by obtaining a plurality of bias values based on at least two space widths according to each of line critical dimensions (CDs) of the designed database patterns and by detecting the shape of the pattern having the optimum bias value. The method applies different space widths to the patterns according to critical dimensions of lines of the patterns of the photo mask to preliminarily detect patterning failure varied according to illuminating systems, sub-films, and thicknesses of resist, and to correct failure of the patterns, such as collapse or bridges of the patterns, generated from the different lengths of patterns lines having the same critical dimension, using different bias values.

Abstract: A mask layout forming method includes designing an original layout in which a diagonal pattern of a first polygon is repeatedly arranged in a diagonal direction relative to a vertical-axis direction. Opposite edge sides of the diagonal pattern of the first polygon are corrected such that second polygons extending in a horizontal-axis direction are stacked at the opposite edge sides of the diagonal pattern of the first polygon to form a stair-shaped layout. The polygons are fractured in the horizontal-axis direction to provide data associated with the corrected layout to an electron beam exposure system. The diagonal pattern of the first polygon defines an active region and a device isolation layer along a 6F2 cell layout or a 4F2 cell layout.

Abstract: A mask layout forming method includes designing an original layout in which a diagonal pattern of a first polygon is repeatedly arranged in a diagonal direction relative to a vertical-axis direction. Opposite edge sides of the diagonal pattern of the first polygon are corrected such that second polygons extending in a horizontal-axis direction are stacked at the opposite edge sides of the diagonal pattern of the first polygon to form a stair-shaped layout. The polygons are fractured in the horizontal-axis direction to provide data associated with the corrected layout to an electron beam exposure system. The diagonal pattern of the first polygon defines an active region and a device isolation layer along a 6F2 cell layout or a 4F2 cell layout.

Abstract: Disclosed is a photo mask used for fabricating a semiconductor device, capable of ensuring a process margin for a photo process in a pattern region where it is difficult to use an assist feature. The photo mask includes a line/space pattern part for forming a line/space pattern on a wafer. The line/space pattern part includes an outermost pattern having a slice pattern so that so that the outermost pattern of the line/space pattern part is divided into two or more pattern segments.