Abstract: A reflection photomask includes a reflection layer on a substrate, an absorber pattern on the reflection layer, and a capping layer on the reflection layer. The capping layer may be selected to decrease a reflectivity of the reflection photomask by less than about 20% of the reflectivity of the reflection layer.

Abstract: A method of manufacturing a capacitor includes sequentially forming a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer over a semiconductor substrate. A first post-annealing of the substrate is performed under an inert atmosphere at a first temperature, and then a second post-annealing is performed at a second temperature. The first and second post annealings can be performed after forming the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination thereof, as long as the second post-annealing is performed after the first post-annealing. The post-annealings are not necessarily performed in a same place or stage. The first temperature may be about 600° C. to 900° C., and the second temperature about 100° C. to 600° C. As a result, the dielectric constant of the high dielectric layer is increased, and leakage current is reduced.

Abstract: Reflection photomasks add a buffer layer including at least one Group VIII metal between a reflection layer and an absorber pattern that is configured to absorb extreme ultraviolet rays therein. In particular, reflection photomasks include a substrate and a reflection layer having multiple sets of alternating films of first and second materials, on the substrate. A buffer layer including at least one Group VIII metal is provided on the reflection layer opposite the substrate. An absorber pattern including material that is patterned in a pattern and that is configured to absorb extreme ultraviolet rays, is provided on the buffer layer opposite the reflection layer. The at least one Group VIII metal preferably is Ru. At least a portion of the Ru buffer layer may be less than about 3 nm thick. Alternatively, the Group VIII metal can include Pt, Ir and/or Pd.

Abstract: A reflection photomask includes a reflection layer on a substrate, an absorber pattern on the reflection layer, and a capping layer on the reflection layer. The capping layer may be selected to decrease a reflectivity of the reflection photomask by less than about 20% of the reflectivity of the reflection layer.

Abstract: A method for manufacturing a capacitor for a semiconductor device, the method includes forming a first interlayer dielectric film pattern on a semiconductor substrate, with the interlayer dielectric film pattern having a first contact hole to expose a portion of the semiconductor substrate through the first contact hole. A contact plug is formed to fill the first contact hole and connect to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion layer pattern. Next a second interlayer dielectric film pattern is formed on the first dielectric film pattern and the first conductive film pattern. The second interlayer dielectric film pattern includes a second contact hole that exposes a top surface of the first conductive film pattern.

Abstract: A method is provided for manufacturing a capacitor of a semiconductor device in which a storage electrode, a high dielectric layer, a plate electrode, and an interdielectric layer are sequentially formed over a semiconductor substrate. This method includes the steps of performing a first post-annealing of the semiconductor substrate under an inert atmosphere at a first temperature and then performing a second post-annealing of the semiconductor substrate at a second temperature. The first and second post annealing steps can be performed after the deposition of the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination of this, so long as the second post-annealing step is performed after the first post-annealing step. The two post-annealing steps do not have to be performed in the same place or at the same stage during the fabrication process. The first temperature is preferably in the range of about 600° C. to 900° C.

Abstract: Reflection photomasks add a buffer layer including at least one Group VIII metal between a reflection layer and an absorber pattern that is configured to absorb extreme ultraviolet rays therein. In particular, reflection photomasks include a substrate and a reflection layer having multiple sets of alternating films of first and second materials, on the substrate. A buffer layer including at least one Group VIII metal is provided on the reflection layer opposite the substrate. An absorber pattern including material that is patterned in a pattern and that is configured to absorb extreme ultraviolet rays, is provided on the buffer layer opposite the reflection layer. The at least one Group VIII metal preferably is Ru. At least a portion of the Ru buffer layer may be less than about 3 nm thick. Alternatively, the Group VIII metal can include Pt, Ir and/or Pd.

Abstract: A capacitor of a semiconductor device includes a first interlayer dielectric film pattern formed on a semiconductor substrate and having a first contact hole therein and a contact plug buried in the first contact hole and electrically connected to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion barrier layer pattern for preventing the oxidization of the diffusion barrier layer pattern. A second interlayer dielectric pattern having a second contact hole exposing the surface of the first conductive film pattern is formed on the first interlayer dielectric film pattern and the first conductive film pattern. A second conductive film pattern used as the lower electrode of a capacitor is buried in the second contact hole and connected to the first conductive film pattern.

Abstract: In accordance with the present invention, a method of fabricating a concave capacitor is provided. The concave capacitor of the present invention includes an adhesion spacer is formed between a concave pattern comprising an interlayer dielectric film and a lower electrode is provided. In the concave capacitor fabricating method, an interlayer dielectric film is formal semiconductor substrate. A concave pattern having a storage node e exposing part of the upper surface of the semiconductor substrate is form by patterning the interlayer dielectric film. An adhesion spacer is formed on t sidewall of the concave pattern exposed by the storage node hole.

Abstract: Integrated circuit capacitors utilize improved sidewall spacers to protect diffusion barrier layers from parasitic oxidation and capacitor electrodes from being overetched. These sidewall spacers comprise a composite of a material such as Al2O3 or Ta2O5 which contacts the diffusion barrier layer and another material such as silicon dioxide, silicon nitride or spin-on-glass. A preferred integrated circuit capacitor comprises a semiconductor substrate, a first interlayer insulating layer having a contact hole therein, on the substrate, and a polysilicon conductive plug in the contact hole. A first capacitor electrode is also provided on the first interlayer insulating layer and extends opposite the conductive plug. To inhibit oxidation of the conductive plug and chemical reaction between the conductive plug and the first capacitor electrode, a diffusion barrier layer is provided between the first capacitor electrode and the conductive plug.

Abstract: A capacitor of a semiconductor device includes a first interlayer dielectric film pattern formed on a semiconductor substrate and having a first contact hole therein and a contact plug buried in the first contact hole and electrically connected to the semiconductor substrate. A diffusion barrier layer pattern is formed on the contact plug, and a first conductive film pattern is formed on the diffusion barrier layer pattern for preventing the oxidization of the diffusion barrier layer pattern. A second interlayer dielectric pattern having a second contact hole exposing the surface of the first conductive film pattern is formed on the first interlayer dielectric film pattern and the first conductive film pattern. A second conductive film pattern used as the lower electrode of a capacitor is buried in the second contact hole and connected to the first conductive film pattern.

Abstract: A microelectronic device includes an insulating layer on a microelectronic substrate wherein the insulating layer has a contact hole therein exposing a portion of the microelectronic substrate. A first capacitor electrode is provided on a surface of the insulating layer opposite the microelectronic substrate and adjacent the contact hole wherein a lower portion of the first capacitor electrode extends into the contact hole below the surface of the insulating layer. A ferroelectric layer is provided on the first capacitor electrode, and a second capacitor electrode is provided on the ferroelectric layer. Related methods and memory devices are also discussed.

Abstract: A microelectronic device includes an insulating layer on a microelectronic substrate wherein the insulating layer has a contact hole therein exposing a portion of the microelectronic substrate. A first capacitor electrode is provided on a surface of the insulating layer opposite the microelectronic substrate and adjacent the contact hole wherein a lower portion of the first capacitor electrode extends into the contact hole below the surface of the insulating layer. A ferroelectric layer is provided on the first capacitor electrode, and a second capacitor electrode is provided on the ferroelectric layer. Related methods and memory devices are also discussed.

Abstract: A method for fabricating a semiconductor device using a high dielectric material as a dielectric film of a capacitor wherein an etch stopping layer such as BST having a good dry etch selectivity with respect to an interlayer insulating film is formed on the adhesion layer formed on an upper electrode. This etch stopping layer prevents the upper electrode of a capacitor from being exposed to be etched during forming a metal contact.

Abstract: Integrated circuit capacitors utilize improved sidewall spacers to protect diffusion barrier layers from parasitic oxidation and capacitor electrodes from being overetched. These sidewall spacers include a composite of a material such as Al.sub.2 O.sub.3 or Ta.sub.2 O.sub.5 which contacts the diffusion barrier layer and another material such as silicon dioxide, silicon nitride or spin-on-glass. A preferred integrated circuit capacitor includes a semiconductor substrate, a first interlayer insulating layer having a contact hole therein, on the substrate, and a polysilicon conductive plug in the contact hole. A first capacitor electrode is also provided on the first interlayer insulating layer and extends opposite the conductive plug. To inhibit oxidation of the conductive plug and chemical reaction between the conductive plug and the first capacitor electrode, a diffusion barrier layer is provided between the first capacitor electrode and the conductive plug.

Abstract: Methods of forming floating-gate ferroelectric random-access-memory (FFRAM) devices include the steps of forming vertically integrated FFRAM unit cells having floating-gate transistors and access transistors positioned at different levels on a semiconductor substrate to increase the density at which the unit cells may be integrated. Preferred methods include the steps of forming a first transistor having opposing floating and control gate electrodes, at a surface of a semiconductor substrate, and then forming a first insulating layer having a first contact hole therein, on the first transistor. The first transistor comprises a layer of ferroelectric material between the floating and control gate electrodes, which can be polarized in respective first and second states to retain logic 1 and logic 0 data. Steps are then performed to form a first electrical interconnect (e.g., conductive plug) in the first contact hole and electrically coupled to the control gate electrode.

Abstract: A method for fabricating an integrated circuit capacitor includes the steps of forming a first electrode on a microelectronic substrate, and plasma treating the first electrode with a with a plasma of a gas including nitrogen and oxygen. A dielectric film is formed on the plasma treated first electrode opposite the microelectronic substrate. A second electrode is formed on the dielectric film opposite the plasma treated first electrode.