Patents by Inventor Byoung Wook Jang

Byoung Wook Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120235307
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Inventors: Jong-Woo Ha, DaeSik Choi, Byoung Wook Jang
  • Publication number: 20120133038
    Abstract: An integrated circuit package system includes a trace frame includes: an encapsulant; a first series of bonding pads along a length of the encapsulant; a second series of the bonding pads along a width of the encapsulant; conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and a first integrated circuit die on the encapsulant and on the conductive traces that extend beyond the first integrated circuit die.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang
  • Patent number: 8138591
    Abstract: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: March 20, 2012
    Assignee: STATS ChipPAC Ltd
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang
  • Publication number: 20110244635
    Abstract: A method for manufacture of an integrated circuit package system includes: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.
    Type: Application
    Filed: June 13, 2011
    Publication date: October 6, 2011
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang, YoungChul Kim
  • Patent number: 7994625
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure die above the internal structure substrate; encapsulating the internal structure die with an internal structure encapsulation to form an internal structure package; forming an internal structure protrusion in the internal structure encapsulation below the internal structure substrate cavity; mounting the internal structure package above a substrate; and encapsulating the internal structure package above the substrate with an encapsulation.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, DeokKyung Yang, Jong-Woo Ha, Byoung Wook Jang, JaeSick Bae, Seung Won Kim
  • Patent number: 7968981
    Abstract: An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: June 28, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang, YoungChul Kim
  • Publication number: 20110062599
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base package substrate; mounting a flip chip integrated circuit die on the base package substrate; applying a flip chip protective layer on the flip chip integrated circuit die including covering only a back side of the flip chip integrated circuit die; and mounting an upper package on the base package substrate including positioning an upper package substrate adjacent to the flip chip protective layer.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Inventors: Joon Dong Kim, Seong Won Park, Byoung Wook Jang
  • Patent number: 7871861
    Abstract: A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: January 18, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, Junwoo Myung, Byoung Wook Jang
  • Patent number: 7863737
    Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
  • Publication number: 20100244217
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 30, 2010
    Inventors: Jong-Woo Ha, DaeSik Choi, Byoung Wook Jang
  • Publication number: 20100123232
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure die above the internal structure substrate; encapsulating the internal structure die with an internal structure encapsulation to form an internal structure package; forming an internal structure protrusion in the internal structure encapsulation below the internal structure substrate cavity; mounting the internal structure package above a substrate; and encapsulating the internal structure package above the substrate with an encapsulation.
    Type: Application
    Filed: November 18, 2008
    Publication date: May 20, 2010
    Inventors: DaeSik Choi, DeokKyung Yang, Jong-Woo Ha, Byoung Wook Jang, JaeSick Bae, Seung Won Kim
  • Patent number: 7683467
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; stacking a first device over the support structure; stacking a second device over the first device; connecting the first device and the second device to the lead-finger system; stacking a dummy device over the second device; and exposing a support structure bottom side and a dummy device top side for thermal dissipation.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: March 23, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Byoung Wook Jang, Young Cheol Kim, Koo Hong Lee
  • Publication number: 20090321908
    Abstract: A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.
    Type: Application
    Filed: June 25, 2008
    Publication date: December 31, 2009
    Inventors: Sungmin Song, Junwoo Myung, Byoung Wook Jang
  • Publication number: 20090283889
    Abstract: An integrated circuit package system includes: providing a heat spreader; attaching an upper substrate to the heat spreader, the upper substrate having an upper through-opening provided therein; attaching a top semiconductor die to the heat spreader through the upper through-opening, the top semiconductor die having a top die interconnect to the upper substrate; attaching a base substrate to the upper substrate, the base substrate having a base through-opening provided therein larger than the upper through-opening; and attaching an external interconnect connected to the base substrate.
    Type: Application
    Filed: May 16, 2008
    Publication date: November 19, 2009
    Inventors: Byoung Wook Jang, Junwoo Myung, JoHyun Bae
  • Publication number: 20090258494
    Abstract: An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 15, 2009
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang, YoungChul Kim
  • Publication number: 20080171405
    Abstract: An integrated circuit package system includes forming an integrated circuit stack having a bottom non-active side and a top non-active side; connecting an internal interconnect between a lead, having a top side and a bottom side, and the integrated circuit stack; and forming an encapsulation, having both a non-elevated portion and an elevated portion, around the integrated circuit stack and the internal interconnect with the top side exposed at the non-elevated portion, and with the bottom side, the bottom non-active side, and the top non-active side exposed.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 17, 2008
    Inventors: Jae Hak Yee, Byoung Wook Jang
  • Publication number: 20080135989
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a support structure and a lead-finger system; stacking a first device over the support structure; stacking a second device over the first device; connecting the first device and the second device to the lead-finger system; stacking a dummy device over the second device; and exposing a support structure bottom side and a dummy device top side for thermal dissipation.
    Type: Application
    Filed: December 7, 2006
    Publication date: June 12, 2008
    Applicant: STATS ChipPAC Ltd.
    Inventors: Byoung Wook Jang, Young Cheol Kim, Koo Hong Lee
  • Publication number: 20080073770
    Abstract: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 27, 2008
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang
  • Publication number: 20070235869
    Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.
    Type: Application
    Filed: April 1, 2006
    Publication date: October 11, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang