Patents by Inventor Byoung Yool JEON

Byoung Yool JEON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package and method of manufacturing the same
    Patent number: 9564411
    Abstract: Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 7, 2017
    Assignee: NEPES CO., LTD
    Inventors: Yun-Mook Park, Byoung-Yool Jeon
  • SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140353823
    Abstract: Disclosed herein is a semiconductor package having a fan-out structure in which a semiconductor chip is buried by an encapsulation member and an external connection member is disposed below the buried semiconductor chip. The semiconductor package includes an embedded rewiring pattern layer, an upper semiconductor chip disposed above the embedded rewiring pattern layer, an upper encapsulation member encapsulating the upper semiconductor chip, a lower semiconductor chip disposed below the embedded rewiring pattern layer, and a lower encapsulation member encapsulating the lower semiconductor chip to prevent exposure thereof.
    Type: Application
    Filed: December 28, 2012
    Publication date: December 4, 2014
    Applicant: NEPES CO., LTD.
    Inventors: Yun-Mook Park, Byoung-Yool Jeon
  • Wafer level semiconductor package and fabrication method thereof
    Patent number: 8421211
    Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.
    Type: Grant
    Filed: June 27, 2010
    Date of Patent: April 16, 2013
    Assignee: Nepes Corporation
    Inventors: In Soo Kang, Gi Jo Jung, Byoung Yool Jeon
  • WAFER LEVEL SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF
    Publication number: 20110260336
    Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.
    Type: Application
    Filed: June 27, 2010
    Publication date: October 27, 2011
    Applicant: NEPES CORPORATION
    Inventors: In Soo KANG, Gi Jo JUNG, Byoung Yool JEON