Patents by Inventor Byoung Chan Oh
Byoung Chan Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9741434Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.Type: GrantFiled: September 4, 2013Date of Patent: August 22, 2017Assignees: SK HYNIX INC., KABUSHIKI KAISHA TOSHIBAInventors: Akira Katayama, Masahiro Takahashi, Tsuneo Inaba, Hyuck Sang Yim, Dong Keun Kim, Byoung Chan Oh, Ji Wang Lee
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Patent number: 9542124Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.Type: GrantFiled: March 19, 2014Date of Patent: January 10, 2017Assignee: SK hynix Inc.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Patent number: 9484091Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.Type: GrantFiled: March 3, 2015Date of Patent: November 1, 2016Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Masahiro Takahashi, Akira Katayama, Dong Keun Kim, Byoung Chan Oh
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Patent number: 9450575Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.Type: GrantFiled: February 17, 2015Date of Patent: September 20, 2016Assignee: SK hynix Inc.Inventor: Byoung-Chan Oh
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Patent number: 9437289Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.Type: GrantFiled: March 19, 2014Date of Patent: September 6, 2016Assignee: SK hynix Inc.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Patent number: 9413236Abstract: A voltage converter includes a power supply circuit configured to generate an output voltage based on an input voltage in response to a control signal, and a power supply control circuit configured to generate the control signal based on a reference clock signal and the output voltage.Type: GrantFiled: December 16, 2014Date of Patent: August 9, 2016Assignees: SK HYNIX INC., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITYInventors: Jin-Hyuk Kim, Dong-Hoon Jung, Kyung-Ho Ryu, Seong-Ook Jung, Byoung-Chan Oh
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Patent number: 9384828Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to generate multi-bit digital data corresponding to a total current which is acquired by summing currents flowing through the plurality of variable resistance elements.Type: GrantFiled: February 26, 2014Date of Patent: July 5, 2016Assignee: SK hynix Inc.Inventor: Byoung-Chan Oh
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Patent number: 9368180Abstract: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.Type: GrantFiled: October 9, 2014Date of Patent: June 14, 2016Assignee: SK hynix Inc.Inventors: Byoung-Chan Oh, Dong-Keun Kim
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Publication number: 20160072493Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.Type: ApplicationFiled: February 17, 2015Publication date: March 10, 2016Inventor: Byoung-Chan Oh
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Publication number: 20150302925Abstract: Disclosed is an electronic device including a semiconductor memory. The semiconductor memory includes a bit line, a source line, a plurality of resistive memory cells among which a selected resistive memory cell forms a current path between the bit line and the source line, a sense amplifier suitable for sensing data of the bit line in an active operation, a latch suitable for latching data sensed by the sense amplifier in the active operation, a write control unit suitable for comparing data latched in the latch with write data in a write operation, and a write driver suitable for driving the bit line and the source line based on a comparison result of the write control unit and the write data in the write operation.Type: ApplicationFiled: December 4, 2014Publication date: October 22, 2015Inventors: Byoung-Chan OH, Ji-Hyae BAE, Katsuyuki FUJITA, Yutaka SHIRAI
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Patent number: 9154140Abstract: A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.Type: GrantFiled: December 18, 2014Date of Patent: October 6, 2015Assignees: SK Hynix Inc., Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Dong-Hoon Jung, Jin-Hyuk Kim, Kyung-Ho Ryu, Seong-Ook Jung, Byoung-Chan Oh
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Publication number: 20150263740Abstract: A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.Type: ApplicationFiled: December 18, 2014Publication date: September 17, 2015Inventors: Dong-Hoon JUNG, Jin-Hyuk KIM, Kyung-Ho RYU, Seong-Ook JUNG, Byoung-Chan OH
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Publication number: 20150194891Abstract: A voltage converter includes a power supply circuit configured to generate an output voltage based on an input voltage in response to a control signal, and a power supply control circuit configured to generate the control signal based on a reference clock signal and the output voltage.Type: ApplicationFiled: December 16, 2014Publication date: July 9, 2015Inventors: Jin-Hyuk KIM, Dong-Hoon JUNG, Kyung-Ho RYU, Seong-Ook JUNG, Byoung-Chan OH
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Publication number: 20150179252Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.Type: ApplicationFiled: March 3, 2015Publication date: June 25, 2015Inventors: Masahiro TAKAHASHI, Akira KATAYAMA, Dong Keun KIM, Byoung Chan OH
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Publication number: 20150103587Abstract: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.Type: ApplicationFiled: October 9, 2014Publication date: April 16, 2015Inventors: Byoung-Chan Oh, Dong-Keun Kim
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Patent number: 9001559Abstract: According to one embodiment, a resistance change memory includes a memory cell, a sense amplifier and a global bit line. The memory cell is disposed at a location where a local bit line and a word line intersect each other. The memory cell is connected to both the local bit line and the word line. The sense amplifier reads data stored on the memory cell by supplying a read current to the memory cell. The global bit line is connected between the local bit line and the sense amplifier. The global bit line feeds the read current supplied by the sense amplifier to the local bit line. The sense amplifier charges the global bit line, before the local bit line and the global bit line are connected to each other.Type: GrantFiled: September 4, 2013Date of Patent: April 7, 2015Inventors: Masahiro Takahashi, Akira Katayama, Dong Keun Kim, Byoung Chan Oh
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Publication number: 20150049536Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.Type: ApplicationFiled: March 19, 2014Publication date: February 19, 2015Applicant: SK HYNIX INC.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Publication number: 20140337568Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.Type: ApplicationFiled: March 19, 2014Publication date: November 13, 2014Applicant: SK HYNIX INC.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Patent number: 8879339Abstract: A write control device includes a switching unit configured to selectively supply a write current in response to a driving control signal, a driving unit configured to supply a driving current to a memory cell corresponding to the write current applied through the switching unit, and an over-driving control unit coupled to an output node of the driving unit and configured to over-drive the output node in response to the driving control signal.Type: GrantFiled: August 22, 2012Date of Patent: November 4, 2014Assignee: SK Hynix Inc.Inventors: Byoung Chan Oh, Yoon Jae Shin
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Publication number: 20140286075Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.Type: ApplicationFiled: September 4, 2013Publication date: September 25, 2014Inventors: Akira KATAYAMA, Masahiro TAKAHASHI, Tsuneo INABA, Hyuck Sang YIM, Dong Keun KIM, Byoung Chan OH, Ji Wang LEE