Patents by Inventor Byoung-Hak Hong
Byoung-Hak Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894376Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: GrantFiled: March 10, 2021Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Won Ha, Byoung-Hak Hong
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Publication number: 20210202482Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: ApplicationFiled: March 10, 2021Publication date: July 1, 2021Inventors: Dae-won Ha, Byoung-hak Hong
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Patent number: 10978453Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: GrantFiled: November 30, 2018Date of Patent: April 13, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Byoung-Hak Hong
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Patent number: 10804403Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.Type: GrantFiled: June 11, 2019Date of Patent: October 13, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daewon Ha, Seungseok Ha, Byoung Hak Hong
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Publication number: 20190312145Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.Type: ApplicationFiled: June 11, 2019Publication date: October 10, 2019Inventors: DAEWON HA, SEUNGSEOK HA, BYOUNG HAK HONG
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Patent number: 10361310Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.Type: GrantFiled: March 20, 2017Date of Patent: July 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Daewon Ha, Seungseok Ha, Byoung Hak Hong
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Publication number: 20190109137Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: DAE-WON HA, BYOUNG-HAK HONG
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Publication number: 20190035788Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities.Type: ApplicationFiled: October 5, 2018Publication date: January 31, 2019Inventors: MUN-HYEON KIM, SOO-HYEON KIM, BYOUNG-HAK HONG, KEUN-HWI CHO, TOSHINORI FUKAI, SHIGENOBU MAEDA, HIDENOBU FUKUTOME
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Patent number: 10177148Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: GrantFiled: February 16, 2017Date of Patent: January 8, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dae-Won Ha, Byoung-Hak Hong
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Publication number: 20180040620Abstract: An integrated circuit device includes: a plurality of channel regions spaced apart from each other in an active region; a plurality of source/drain regions; an insulating structure on the active region, the insulating structure defining a plurality of gate spaces; a first gate stack structure in a first of the gate spaces, the first gate stack structure including a first work function metal-containing layer; and an isolation stack structure in a second of the gate spaces that is adjacent the first of the gate spaces, the isolation stack structure having a different stack structure from the first gate stack structure and being configured to electrically isolate a portion of the active region.Type: ApplicationFiled: February 16, 2017Publication date: February 8, 2018Inventors: DAE-WON HA, BYOUNG-HAK HONG
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Publication number: 20180040699Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.Type: ApplicationFiled: March 20, 2017Publication date: February 8, 2018Inventors: DAEWON HA, SEUNGSEOK HA, BYOUNG HAK HONG
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Patent number: 9773785Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.Type: GrantFiled: July 26, 2016Date of Patent: September 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu Baik Chang, Byoung Hak Hong, Yoon Suk Kim, Seung Hyun Song
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Patent number: 9711505Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.Type: GrantFiled: April 8, 2016Date of Patent: July 18, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Hak Hong, Bon-Woong Koo, Sung-Il Park, Kyu-Baik Chang, Keun-Hwi Cho, Dae-Won Ha
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Publication number: 20170162574Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type impurities.Type: ApplicationFiled: July 13, 2016Publication date: June 8, 2017Inventors: MUN-HYEON KIM, SOO-HYEON KIM, BYOUNG-HAK HONG, KEUN-HWI CHO, TOSHINORI FUKAI, SHIGENOBU MAEDA, HIDENOBU FUKUTOME
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Publication number: 20170162566Abstract: A semiconductor device includes first and second fins on first and second regions of a substrate, a first trench overlapping a vertical end portion of the first fin and including first upper and lower portions, the first upper and lower portions separated by an upper surface of the first fin, a second trench overlapping a vertical end portion of the second fin and including second upper and lower portions separated by an upper surface of the second fin, a first dummy gate electrode including first metal oxide and filling layers, the first metal oxide layer filling the first lower portion of the first trench and is along a sidewall of the first upper portion of the first trench, and a second dummy gate electrode filling the second trench and including second metal oxide and filling layers, the second metal oxide layer extending along sidewalls of the second trench.Type: ApplicationFiled: July 26, 2016Publication date: June 8, 2017Inventors: Kyu Baik CHANG, Byoung Hak HONG, Yoon Suk KIM, Seung Hyun SONG
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Publication number: 20170033217Abstract: A semiconductor device includes a gate structure on a substrate. The gate structure includes a first gate insulation pattern, a conductive pattern for controlling a threshold voltage, a first gate electrode and a first mask sequentially stacked. A dummy gate structure is spaced apart from the gate electrode. The dummy gate structure includes a first stressor pattern including titanium oxide. Source/drain regions are adjacent to the gate structure. The source/drain regions are doped with p-type impurities. The first stressor pattern may apply a stress onto the channel region of a transistor, and consequently the transistor having good electrical characteristics may be obtained.Type: ApplicationFiled: April 8, 2016Publication date: February 2, 2017Inventors: BYOUNG-HAK HONG, BON-WOONG KOO, SUNG-IL PARK, KYU-BAIK CHANG, KEUN-HWI CHO, DAE-WON HA
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Publication number: 20170033107Abstract: A semiconductor device includes a substrate including at least one metal-oxide-semiconductor field-effect transistor (MOSFET) region defined by a device isolation layer and having an active pattern extending in a first direction on the MOSFET region, a gate electrode intersecting the active pattern on the substrate and extending in a second direction intersecting the first direction, and a first gate separation pattern adjacent to the MOSFET region when viewed from a plan view and dividing the gate electrode into segments spaced apart from each other in the second direction. The first gate separation pattern has a tensile strain when the MOSFET region is a P-channel. MOSFET (PMOSFET) region. The first gate separation pattern has a compressive strain when the MOSFET region is an N-channel MOSFET (NMOSFET) region.Type: ApplicationFiled: May 20, 2016Publication date: February 2, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Byoung Hak HONG, Sungil Park, Toshinori Fukai, Shigenobu Maeda, Sada-aki Masuoka, Sanghyun Lee, Keon Yong Cheon, Hock-Chun Chin
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Patent number: 9331199Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.Type: GrantFiled: March 25, 2015Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Keun-Hwi Cho, Sung-Il Park, Byoung-Hak Hong, Toshinori Fukai, Mun-Hyeon Kim, Woong-Gi Kim, Sue-Hye Park, Dong-Won Kim, Dae-Won Ha
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Publication number: 20160043222Abstract: Provided is a semiconductor device to which a pattern structure for performance improvement is applied.Type: ApplicationFiled: March 25, 2015Publication date: February 11, 2016Inventors: Keun-Hwi Cho, Sung-II Park, Byoung-Hak Hong, Toshinori Fukai, Mun-Hyeon Kim, Woong-Gi Kim, Sue-Hye Park, Dong-Won Kim, Dae-Won Ha