Abstract: A display device includes a display module and a support plate disposed under the display module. The support plate includes a flat portion, a flexible portion that extends from the flat portion and that is folded such that a portion is disposed under the flat portion, and a plurality of protruding bars that protrude downward from the flexible portion, and a plurality of grooves is defined in an upper surface of the flexible portion and overlaps the plurality of protruding bars.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: Display apparatus includes LEDs, bottom chassis to accommodate the LEDs; and reflective member disposed on the bottom chassis. The reflective member includes a reflective bottom portion, and a reflective inclined portion obliquely formed to face a rear surface of the display panel which includes first regions that respectively correspond to LEDs located adjacent to the reflective inclined portion, and second regions each provided between two neighboring first regions and has a reflective characteristic different from a reflective characteristic of a neighboring first region. Second regions and neighboring first regions are on the reflective inclined portion having a uniform incline angle with respect to a side edge of the reflective bottom portion, the first regions include a group of light adjusting members, and the group of light adjusting members of each of the first regions is disposed to correspond to one of the LEDs disposed adjacent to the reflective inclined portion.

Abstract: Disclosed are a content providing apparatus, a method of controlling the same, and a recording medium thereof, the content providing apparatus including: a transmitter configured to transmit data to a display apparatus; and a processor configured to control the transmitter to transmit content data and additional data, relating to image attributes of the content data and having a fixed value corresponding to at least one section, among a plurality of sections of the content data, to the display apparatus based on a command received from a user to playback image content at a predetermined speed. Thus, it is possible to solve a problem of flickering or an error in brightness of a screen at a variable-speed playback of dynamic HDR content.

Abstract: An electronic apparatus is provided. The electronic apparatus according to an example embodiment includes a communication interface and a processor configured to provide a video content and dynamic metadata corresponding to each content section of the video content to an external display apparatus through the communication interface, each content section comprising a plurality of frames, wherein the processor is further configured to transmit the dynamic metadata to the external display apparatus on a frame-by-frame basis, and based on a graphic content being activated, provide data to the display apparatus by converting dynamic metadata corresponding to a content section where the graphic content is activated into static metadata during a plurality of frames.

Abstract: Disclosed are a content providing apparatus, a method of controlling the same, and a recording medium thereof, the content providing apparatus including: a transmitter configured to transmit data to a display apparatus; and a processor configured to control the transmitter to transmit content data and additional data, relating to image attributes of the content data and having a fixed value corresponding to at least one section, among a plurality of sections of the content data, to the display apparatus based on a command received from a user to playback image content at a predetermined speed. Thus, it is possible to solve a problem of flickering or an error in brightness of a screen at a variable-speed playback of dynamic HDR content.

Abstract: An electronic apparatus is provided. The electronic apparatus according to an example embodiment includes a communication interface and a processor configured to provide a video content and dynamic metadata corresponding to each content section of the video content to an external display apparatus through the communication interface, each content section comprising a plurality of frames, wherein the processor is further configured to transmit the dynamic metadata to the external display apparatus on a frame-by-frame basis, and based on a graphic content being activated, provide data to the display apparatus by converting dynamic metadata corresponding to a content section where the graphic content is activated into static metadata during a plurality of frames.

Abstract: The disclosure is related tracking area management in a femtocell network. A mobility management entity may receive, from a femtocell base station, macrocell tracking area information associated with the femtocell base station. The mobility management entity may combine the received macrocell tracking area information with femtocell tracking area information associated with the femtocell base station and storing the combined tracking area information as integrated tracking area information.

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

Abstract: Provided are apparatus and method for controlling handover to prevent femtocell interference. The apparatus may include an event receiving module, a handover determining module, and an inter-frequency processing module. The event receiving module may be configured to receive a control message from user equipment. The handover determining module may be configured to analyze the received control message and determine whether the control message includes a request of inter-cell handover from a first cell base station of the first cell to a second cell base station of one of the second cells. The inter-frequency processing module may be configured to perform inter-frequency handover using an unshared frequency when the handover determining module determines that the control message includes the request of inter-cell handover.

Abstract: A method, system and apparatus for connecting multiple memory device dies 51-54 to a substrate 56 which requires no trace between dies. A first embodiment assigns the connections of a memory device die 51 to be matched with other memory device dies 52-54 when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the buses 57,58 between memory device dies 51,52,53 are reduced. The number of vias 57,58,59 is reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG. 7 arranges the dies in a closed loop.

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

Abstract: Described embodiments provide for handover in a long term evolution (LTE) communication network. A LTE macrocell base station may receive a measurement report from user equipment while providing a communication service to the user equipment located within a service area of the LTE macrocell base station, and determine whether or not the neighbor cell is a LTE macrocell or a LTE femtocell based on the measurement report. The LTE macrocell base station may initiate hand-over of the user equipment to a neighbor WCDMA macrocell base station when the neighbor cell is determined as the LTE femtocell.

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices 2, 3, connected to a logic device 1, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device 1 having capability to analyze and compensate for differing delays to the stacked devices 2,3,4,5 stacking multiple dice divided into partitions serviced by multiple buses 21,22 connected to a logic die 1, to increase throughput between the devices 2,3 and logic 1 device allowing large scale integration of memory with self-healing capability.

Abstract: Provided are apparatus and method for controlling handover to prevent femtocell interference. The apparatus may include an event receiving module, a handover determining module, and an inter-frequency processing module. The event receiving module may be configured to receive a control message from user equipment. The handover determining module may be configured to analyze the received control message and determine whether the control message includes a request of inter-cell handover from a first cell base station of the first cell to a second cell base station of one of the second cells. The inter-frequency processing module may be configured to perform inter-frequency handover using an unshared frequency when the handover determining module determines that the control message includes the request of inter-cell handover.

Abstract: A dynamic random access memory device is described. A first array has a first plurality of bitlines, each coupled to a column of memory cells. A second has a second plurality of bitlines, each coupled to a column of memory cells. Sense amplifiers are selectively connectable in an open bitline configuration to at least one bitline of the first plurality of bitlines and at least one complementary bitline of the second plurality of bitlines. A voltage supply having a voltage VBL corresponding to a bitline precharge voltage is selectively connectable to each bitline. Logic selectively connects each bitline and the complementary bitline to one of a sense amplifier and the voltage supply during a read operation. Each bitline connected to the sense amplifier is adjacent to a bitline concurrently connected to the voltage supply. A method is also described.

Abstract: Provided are apparatus and method for setting a cyclic prefix length according to a type of a base station. The apparatus may include a memory, a receiver, a selector, and an inserter. The receiver may be configured to store and to manage a plurality of prefix lengths associated with base station types. The receiver may be configured to receive base station information from a base station. The selector may be configured to select a prefix length from the plurality of prefix length based on the received base station information. The inserter may be configured to insert a cyclic prefix having the determined prefix length in a guard interval of a transmission frame.

Abstract: A semiconductor memory device, including: a memory cell connected to a first bitline and associated with a second bitline; a sense amplifier, including a first input/output node and a second input/output node; and an isolator connected to the bitlines and to the input/output nodes, the isolator being configured to carry out bitline isolation during a refresh operation of the memory cell, where the bitline isolation includes electrically disconnecting the first bitline from the first input/output node and electrically disconnecting the second bitline from the second input/output node, followed by: electrically re-connecting the first bitline to the first input/output node while the second bitline remains electrically disconnected from the second input/output node.