Abstract: A method of moving blocks of pixel data, including window-identifying data, from a source area to a destination area within a frame buffer in a computer graphics system comprises the steps of: reading a block of pixel data from the source area into a pixel cache memory; combining source tiles with destination tiles in the cache; comparing pixel window identifiers read from the frame buffer with a pixel window identifier previously stored in the memory to determine whether the pixel window identifiers read from the frame buffer match the previously stored pixel window identifier; discarding each pixel whose corresponding window identifier does not match the previously stored window identifier; and updating the frame buffer with the pixel data not discarded.

Abstract: Pixel arithmetic and logical units for rendering pixels in graphics systems. Circuits for performing arithmetic operations on raster scan data are provided. The circuits comprise opcode registers for selecting an arithmetic function which transforms pixel value data corresponding to graphics primitives, multiplication circuits interfaced with the opcode registers for multiplying graphics operators with graphics data to obtain transform pixel value data, combining circuits interfaced with the multiplication circuits for adding transform pixel value data to existing pixel value data and processing circuitry interfaced with the combining circuitry for storing overflow data from the combining circuitry when adding transform pixel data overflows the combining circuitry.

Abstract: Methods and apparatus for providing pixel brightness correction in monitors. The methods and apparatus disclosed herein provide significant cost reductions in gamma correction circuitry by first degamma correcting pixel value data stored on a frame buffer, and then gamma correcting the degamma corrected pixel value data before the data is stored back on the frame buffer. Circuits for providing pixel brightness correction in a monitor comprise logic circuits for generating upper bits of a data word representing pixel intensity, shifter circuits interfaced with the logic circuits for generating lower bits of the data word representing pixel intensity, and combining circuits interfaced with the logic circuits and the shifter circuits for generating intermediate bits of the data word representing pixel intensity.