Patents by Inventor Byron D. Harris

Byron D. Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210042055
    Abstract: A plurality of generators that each correspond to a respective one of a plurality of cursors associated with the plurality of memory devices are identified. A sequence of logical unit numbers (LUNs) of a plurality of sequences of LUNs are generated for each of the cursors based on a respective generator corresponding to the plurality of cursors. Each of the cursors are directed to perform a memory operation on a set of LUNs in an order provided by the sequence of LUNs that is associated with each of the plurality of cursors.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
  • Patent number: 10860243
    Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 8, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
  • Publication number: 20200278927
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Inventors: Byron D. Harris, Karl D. Schuh
  • Patent number: 10691592
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: June 23, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Byron D. Harris, Karl D. Schuh
  • Publication number: 20200174693
    Abstract: Each of a multiple cursors is assigned a respective generator of multiple generators. The cursors are used to perform an operation on a set of logical unit numbers (LUN) associated with memory devices. Multiple sequences of LUNs are identified based on the generators. Each of the cursors is associated with one of the sequences of LUNs. The operation on the set of LUNs associated with the memory devices is performed using the sequences of LUNs. The operation on the set of LUNs is performed in an order provided by the sequences of LUNs to reduce a probability of collision by the cursors in the performance of the operation.
    Type: Application
    Filed: November 30, 2018
    Publication date: June 4, 2020
    Inventors: Daniel A. Boals, Karl D. Schuh, Byron D. Harris
  • Publication number: 20200133849
    Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device identifying a namespace identifier associated with a first write instruction from a host process and combining the namespace identifier with a namespace offset included in the first write instruction to form a logical address. The logical address is translated into a physical address and included in a second write instruction along with data to be written and the physical address. The second write instruction is sent to a memory component causing the data to be written at the physical address, and the logical address to be stored as metadata associated with the data. The logical address may be translated using a namespace table and one or more translation tables, where the namespace table has entries including a starting location and size of a namespace in a translation table.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Byron D. Harris, Karl D. Schuh
  • Publication number: 20200104251
    Abstract: A portion of a logical block address to physical block address (“L2P”) translation map may be identified. A last snapshot of the portion of the L2P translation map may be identified. One or more write operations may be determined, where the write operations are associated with logical block addresses of the portion of the L2P translation map. The write operations may have been performed after the last snapshot of the portion of the L2P translation map was stored. An address on the portion of the L2P translation map may be updated by a processing device based on the determined one or more write operations and the last snapshot of the portion of the L2P translation map.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Daniel A. Boals, Byron D. Harris, Karl D. Schuh, Amy L. Wohlschlegel