Abstract: Systems and methods are disclosed including a method comprising sending, to a first central processing unit (CPU) of a memory subsystem controller, by a second CPU of the memory subsystem controller, an address range; responsive to detecting an expiration of a timer and determining the first CPU is in an idle state, retrieving, by the first CPU, a log file stored at the address range; and sending, by the first CPU, the log file to a host system.

Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Abstract: Systems and methods are disclosed for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. The memory sub-system controller can include multiple CPUs which can be employed to perform different tasks. The memory sub-system controller can employ one of the frontend CPUs as a monitoring CPU capable of executing a data-gathering task to retrieve system state information from another CPU.

Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.

Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Abstract: A data item is programmed to a first set of physical management units (MUs) associated with a memory sub-system in accordance with a first pass programming operation of a multi-pass programming scheme. An entry of a data structure is updated to include a mapping that associates a first physical address associated with the first set of physical MUs with a set of virtual MUs associated with the memory sub-system. A detection is made that a second pass programming operation of the multi-pass programming scheme is initiated to program the data item to a second set of physical MUs associated with the memory sub-system. Responsive to the detecting, the entry of the data structure is updated to include an additional mapping that associates the set of virtual MUs with a second physical address associated with the second set of physical MUs.

Abstract: Apparatuses and methods for read source determination are provided. One example apparatus can include a controller configured to determine a source for read requests and to direct read requests for a first portion of data to a first block of single level memory cells in response to an amount of a second portion of data written to a second block of single level memory cells being less than a threshold amount, and direct read requests for the first portion of data to a first block of quad level memory cells in response to the amount of the second portion of data written to the second block of single level memory cells being at least the threshold amount.

Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address.

Abstract: A processing device in a memory sub-system performs a first pass of a multi-pass programming operation to coarsely program a first wordline, performs a second pass to coarsely program a second wordline adjacent to the first wordline, performs a third pass of a multi-pass programming operation to finely program the first wordline, performs a fourth pass of a multi-pass programming operation to coarsely program a third wordline adjacent to the second wordline, performs a fifth pass of a multi-pass programming operation to finely program the second wordline, and responsive to determining that at least the second wordline has been finely programmed, performs a read verify operation on one or more cells associated with the first wordline.

Abstract: Methods, systems, and devices for adaptive wear leveling for a memory system are described. A memory system may implement an adaptive rate for performing various wear leveling operations, such as an adaptive rate for performing wear leveling evaluations, or an adaptive rate for performing wear leveling data transfers, among other examples. For example, a memory system may begin with or default to performing wear leveling operations in accordance with a relatively slower rate, and adjust (e.g., accelerate) wear leveling operations based on detecting a relatively greater demand to perform wear leveling operations. In some such examples, wear leveling operations may be capped at a rate (e.g., a maximum rate), which may limit a degradation of memory system performance while performing wear leveling operations. As wear distribution improves, the memory system may adjust (e.g., decelerate) wear leveling operations.

Abstract: Methods, systems, and devices for plane balancing in a memory system are described. A memory system may select a memory die for writing a set of data. The memory die may include a plurality of planes each of which may include a respective plurality of blocks of memory cells. Based on selecting the memory die, the memory system may determine a first plane of the plurality of planes that has a first quantity of blocks with an availability status and a second plane of the plurality of planes that has a second quantity of blocks with the availability status. The memory system may write the set of data to the plurality of planes, excluding at least the first plane, based at least in part on the first quantity of blocks and the second quantity of blocks.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.

Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address.

Abstract: Systems and methods are disclosed including a method comprising sending, by a monitored central processing unit (CPU) to a monitoring CPU of a memory sub-system controller, an address range of a logging data structure stored within a local memory component of the monitored CPU; storing, in the logging data structure by the monitored CPU, a log file comprising system state information associated with one or more tasks performed by the monitored CPU; executing, by the monitoring CPU, a data-gathering task to retrieve the log file from the logging data structure; and sending, by the monitoring CPU, the log file to a host system.

Abstract: A plurality of generators that each correspond to a respective one of a plurality of cursors associated with the plurality of memory devices are identified. A sequence of logical unit numbers (LUNs) of a plurality of sequences of LUNs are generated for each of the cursors based on a respective generator corresponding to the plurality of cursors. Each of the cursors are directed to perform a memory operation on a set of LUNs in an order provided by the sequence of LUNs that is associated with each of the plurality of cursors.

Abstract: Systems and methods for storing and validating namespace metadata are disclosed. An exemplary system includes a memory component and a processing device receiving a first read instruction from a host process. The first read instruction includes a namespace offset. A first logical address is generated by combining a namespace identifier for the namespace assigned to the host process and the namespace offset. The first logical address is translated into a first physical address using a plurality of hierarchical tables. A second read instruction, which includes the first physical address and the first logical address, is generated. The second read instruction is sent to a memory component. The memory component validates the translation of the first logical address by comparing the first logical address in the second read instruction to metadata associated with data to be read at the first physical address.

Abstract: A zone is loaded onto a first memory component of a storage system, wherein the zone comprises one or more regions of data blocks comprising a first plurality of logical block addresses (LBAs), and a snapshot of each of the one or more regions is stored on a second memory component of the storage system and is associated with a version identifier. A particular version identifier associated with a respective snapshot of a region is identified, and a set of journals stored on the second memory component are identified, wherein the set of journals comprise a second plurality of LBAs mapped to a second plurality of physical block addresses.

Abstract: A write command is received, for example, from a host system, which operates on a first logical address range. A read command is received that specifies a second logical address range that matches the first logical address range. Responsive to determining that a deallocate command has been received after the write command, zero-filled data is returned in response to the read command.