Abstract: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

Abstract: A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero.

Abstract: A reference circuit includes: (a) a first reference circuit having a reference signal and a ?VBE loop; and (b) a modification circuit using a first voltage to change a first current in the ?VBE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a VBE and a multiplied ?VBE, so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ?VBE loop. The ?VBE loop can be the portion of the circuit involved in generating the ?VBE voltage. Other embodiments are disclosed in this application.

Abstract: A correction circuit (12) for providing an error correction voltage for a voltage reference (11). The voltage reference (11) provides a reference voltage within a predetermined temperature range. The voltage reference prior to correction has a peak magnitude at a temperature T.sub.0 within the predetermined temperature range. A first circuit (13) generates a correction current. Zero current is provided by the first circuit (13) at T.sub.0. A second circuit (14) receives the correction current and provides an output current that is uni-directional or of the same sense above and below T.sub.0. [Means responsive to t] The output current of the second circuit (14) generates a voltage across a resistor (28) that is [combined] added to the reference voltage above and below T.sub.0.

Abstract: An amplifier output stage with minimum circuitry and optimum performance for providing a SAT-to-SAT output voltage signal at an output terminal. The amplifier output stage includes a first transistor having a collector coupled to the output terminal for sourcing current thereto, a base coupled to a first supply voltage terminal, and an emitter coupled to the first supply voltage terminal. A second transistor having a collector coupled to the output terminal for sinking current thereat, a base, and an emitter coupled to a second supply voltage terminal. A third transistor having a collector, a base coupled to the base of the second transistor, and an emitter coupled to the second supply voltage terminal by a first resistor. A fourth transistor having a collector coupled to the first supply voltage terminal, a base coupled to an input terminal, and an emitter coupled to the base of the third transistor.

Abstract: A method for limiting short circuit current flow in a Field Effect Transistor (FET) to limit the power dissipated therein includes sensing a rise in the drain-to-source voltage of the transistor and clamping the gate-to-source voltage to a predetermined adjustable value thereby reducing the magnitude of the short circuit current flow to within the safe operating characteristics of the device. A comparator switch circuit is responsive to the drain-to-source voltage of the FET exceeding a reference voltage value for clamping the gate-to-source voltage to a predetermined reduced voltage. A trimmable resistive network is connected between the gate and the source electrode of the transistor for adjusting the gate to source clamped voltage potential to compensate for variations in transistor transconductances from one transistor to the next that they may be used in conjunction with the electronic circuitry.

Abstract: A voltage translator circuit generates a predetermined output voltage (e.g. one half of the supply voltage) in response to a predetermined input voltage. A pair of matched field effect transistors are coupled in series between first and second sources of supply voltage. The gate of the load transistor is coupled to a reference voltage, and the gate of the drive transistor is coupled to a source of input voltage. When both transistors are subject to the same operating conditions (at a predetermined input voltage level), their effective resistances become equal and the supply voltage is divided in half. The circuit does not depend for its operation upon precise threshold voltages of the devices as long as the devices are matched.

Abstract: A circuit is provided which comprises a push-pull switching stage responsive to applied control signals for alternately establishing high and low output voltage levels at an output of the circuit responsive to control signals which are derived from an applied input logic signal and which is disabled in response to the control signals being disabled for providing a high output impedance at the output. The circuit includes circuitry responsive to an applied disable signal for disabling the control signals while enabling further circuitry, the latter providing a transient current path to improve the transition from the high voltage output level to the high output impedance condition while establishing a pseudo high output impedance at the output of the circuit until the push-pull stage is disabled.

Abstract: A non-volatile bipolar memory using the technique of comparing selectively degraded bipolar transistor's betas or base-to-emitter voltages to a non-degraded transistor's beta or base-to-emitter voltage to generate desired logic output states from the memory.

Abstract: A voltage supply circuit for supplying a regulated output voltage the magnitude and temperature coefficient of which can be independently controlled. A pair of transistors and associated circuitry develop a voltage proportional to the .DELTA.V.sub.BE of the two transistors which are operated at different current densities and sets a first current through the collector of a third transistor which is proportional to .DELTA.V.sub.BE having a positive temperature coefficient (TC). A second current proportional to the negative temperature coefficient base-to-emitter voltage of the third transistor is generated and combined with the first current to produce a third current having a net negative, zero or positive TC. The third current is used to develop a voltage which is combined with the base-to-emitter voltage of the third transistor to produce the output voltage.

Abstract: A circuit that develops a current having a predetermined temperature coefficient includes a pair of transistors which are supplied equal collector currents but which are operated at different current densities to produce a difference voltage between the emitters thereof that has a predetermined temperature coefficient. A third transistor is biased to sink a collector current the value of which is set by the ratio of the difference voltage to the value of a first resistor which is coupled between the collector and base of the third transistor. A second resistor can be coupled between the base and emitter of the third transistor to an output of the circuit whereby the current flowing from the output has a net temperature coefficient that is determined by the ratio of the value of the first resistor to the value of the second resistor.

Abstract: An integrated circuit comprising a series pass transistor for sourcing current from the positive side of a battery to an inductive load includes integrated circuitry for providing a direct current conduction path between ground and the inductive load as the series pass transistor is turned off by the battery being disconnected therefrom during normal operation so that the stored inductive energy of the inductive load is dissipated. The integrated circuitry includes a silicon controlled rectifier (SCR) coupled between the output of the integrated circuit and ground as well as a Zener diode coupled between the gate and anode of the SCR.

Abstract: An overvoltage protection circuit for directing a surge current on an input/output line, in particular, a telephone line, to a ground terminal when the surge current exceeds a predetermined level.

Abstract: A compensation circuit for stabilization of a circuit node coupled to an integrated circuit substrate by a parasitic capacitance of a value C.sub.1 has a displacement current substantially equal to C.sub.1 dv/dt. A switching device having a gain beta can either supply a current to, or draw a current from, the circuit node substantially equal to C.sub.2 .beta. dv/dt which is greater than the displacement current thereby obviating oscillation of an integrated circuit output due to capacitive coupling of the substrate to sensitive circuit nodes.

Abstract: A method is disclosed for eliminating latch-up and analog signal errors in power circuits having a vertical output transistor structure wherein a P-type chip substrate serves as a collector of a saturating vertical PNP transistor. When the P-type substrate rises to V.sub.CC, current is injected into N-type epitaxial layer regions which may then be collected by P-type regions diffused in the epitaxial regions. Circuit problems due to these parasitic currents are avoided by providing dominantly negative feedback for potential latch mechanisms triggered by the injected currents, and providing balancing means to cancel the effects of the injected currents in analog signal paths.

Abstract: A comparator circuit cell has an output which switches between first and second states when an input voltage (or current) reaches a controlled trip point having a controllable positive, zero or negative temperature coefficient. First and second common emitter transistors are forced to operate at different emitter current densities at the trip point thus requiring the operation of a .DELTA.V.sub.BE across a first resistor coupled between the bases of the first and second transistors in order to get the circuit output to switch. The positive temperature coefficient current which flows through the first resistor to generate .DELTA.V.sub.BE is summed at the base of the second transistor with a negative temperature coefficient current flowing through a second resistor. This creates a required input current having a controllable magnitude and temperature coefficient.

Abstract: An integrated circuit and method for biasing an impurity region, in particular an epitaxial layer, to a level substantially equal to a supply voltage level yet exhibiting a high reverse breakdown voltage to negative transients of the supply voltage. The integrated circuit and method is of especial utility in power BIMOS and other applications having the substrate at or near the supply voltage level.

Abstract: A thermal shut-down circuit is provided that is monolithically integrated in a power BIMOS process wherein a vertical power PNP output transistor comprises a P-type substrate as a collector. The circuit compensates for vertical currents injected from the P-substrate into lateral transistors. A first PNP transistor has an emitter connected to a first resistor and conducts a first current. A second PNP transistor has an emitter connected to a second resistor and conducts a second current. A third resistor has one terminal coupled to the emitter of the second transistor. A fourth resistor is coupled in series with an output means, the combination thereof being coupled in parallel with the second and third resistors.

Abstract: Circuitry is provided for current limiting the output current of a power substrate PNP transistor comprised of a plurality of emitters (e.g. 260). A resistor is placed between a fraction of the plurality of emitters (e.g. 8) and a source of supply voltage. When the power device is turned on, the current is drawn through the resistor causing a voltage drop thereacross. This voltage drop is monitored and when it reaches a certain level, a control signal is generated which ultimately results in limiting the conducted current of the power transistor.

Abstract: An integrated current amplifier circuit combining bipolar and MOS technologies provides accurate current gain over a wide voltage supply range. The amplifier circuit includes a current source for providing first and second currents and first and second resistive circuits coupled to the current source for sinking the respective currents supplied therefrom. A feedback transistor connected between the current source and an output of the amplifier circuit provides current feedback to the first resistive circuit to establish the current gain action of the amplifier circuit which becomes a ratio of two resistors times an input current supplied to the second resistive circuit. The ratio of the two resistors can be accurately controlled thereby controlling the current gain of the amplifier circuit. Additionally, an active turn-off circuit requiring no standby bias current is provided to ensure that the feedback transistor is non-conducting when the amplifier is in an off state.