Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.

Abstract: A power multiplexer system including a power mux controller, wherein the power mux controller generates at least one non-regulated control signal; a regulator coupled to the power mux controller, wherein the regulator generates a reference voltage and wherein the reference voltage is used for generating a regulated control signal; and at least one power multiplexer tile coupled to the regulator, wherein each of the at least one power multiplexer tile includes a first branch comprising a first plurality of transistors and a second branch comprising a second plurality of transistors, and wherein enabling or disabling one or more of the first plurality of transistors is based on either the at least one non-regulated control signal or the regulated control signal.

Abstract: Aspects of the disclosure are directed to saving always on (AON) routing of signals across chips, the disclosure includes turning ON a first power signal in a system on a chip (SOC) when a Power ON Reset (PoR) signal is asserted and a clamp control signal is asserted; turning ON a second power signal in the SOC after the first power signal is turned ON; de-asserting the PoR signal after the second power signal is turned ON; latching a logic signal with a LOW clamp keeper cell if the logic signal is at a LOW logic level or with a HIGH clamp keeper cell if the signal is at a HIGH logic level; and de-asserting the second power signal while a first section of the SOC routes the logic signal through a second section of the SOC.