Abstract: An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.

Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.

Abstract: In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.

Abstract: In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity.

Abstract: A method of simulating a circuit parameter such as voltage or current for a dominantly linear circuit by constructing a circuit equation matrix whose elements correspond to nodes of the circuit, decoupling linear and nonlinear contributions to the circuit parameter based on a partition of an inverse matrix of the circuit equation matrix, computing linear and nonlinear components using the decoupled contributions, and combining the nonlinear and linear components to yield a state of the circuit parameter for a given time step. The computation of the nonlinear component includes Newton-Raphson iterations to linearize nonlinear devices of the circuit, wherein the Newton-Raphson technique is applied to the right-hand side of the circuit state matrix equation. The computations are iteratively repeated for successive time steps which are advantageously separated by a constant time interval to avoid further recalculation of the state matrix.

Abstract: A computer implemented method, data processing system, and computer usable program code are provided for reducing a chip package model. Responsive to receiving the chip package model, an inductance and a resistance of the chip package model is measured. The inductance and the resistance are measured using only a set of external nodes of the chip package model. A reduced node resistor model and a reduced node inductor model are created using the inductance and the resistance of the chip package model. A combined reduced node resistor-inductor chip package model is formed by combining the reduced node resistor model and reduced node inductor model.

Abstract: A system and method for estimating propagation noise that is induced by a non-zero noise glitch at the input of the driver circuit. Such propagation noise is a function of both the input noise glitch and the driver output effective capacitive load, which is typically part of the total wiring capacitance due to resistive shielding in deep sub-micron interconnects. The noise-driven effective capacitance solution provided herein also estimates the propagation noise induced by a non-zero noise glitch at the input of the driving gate. Gate propagation noise rules describing a relationship between the output noise properties and the input noise properties and the output loading capacitance are used within the noise-driven effective capacitance process to determine the linear Thevenin model of the driving gate. The linearized Thevenin driver model is then employed to analyze both the propagation noise and the combined coupling and propagation noise typically seen in global signal nets.

Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs: A) 2D scan line algorithm for the collection of adjacent signal and power conductor coordinates; B) In core pair-wise frequency Dependent RL extraction; C) In core equivalent circuit synthesis; D) caching and partitioning RL extraction techniques for run time efficiency; and E) Techniques for synthesizing stable circuits to represent frequency dependent RL circuits for non-mono tonic R12.

Abstract: A method of modeling electromagnetism in an irregular conductive plane, by dividing the surface into a grid of unequal and unaligned rectangles, assigning a circuit node location to a center of each rectangle, and calculating capacitive and inductive parameters based on the center circuit node locations. Rectangulation is accomplished using automated, recursive bisection. Capacitive segments are assigned to each circuit node and coincide with the corresponding rectangles. Inductive segments are assigned between adjacent rectangle pairs, with a width of an inductive segment defined as the common boundary of the corresponding pair of rectangles and the length of the inductive segment defined as the normal distance between circuit nodes of the two rectangles. Placement of the circuit nodes at the centers of the rectangles significantly reduces the number of nodes and segments, and provides a faster yet comprehensive analysis framework.

Abstract: The present invention relates to a method for analyzing the noise prediction within one or more electrical circuits, wherein the electrical circuits have a power mesh grid distribution system that feeds power levels to the electrical circuits that are connected by signal wires. After identifying a driver and receiver electrical circuit to be analyzed, a power block is generated that is associated with the driver and receiver electrical circuit by partitioning an area of a power mesh grid distribution system into a power block that can be modeled with lossy transmission line techniques. Next, signal wires situated between the driver and receiver electrical circuits are partitioned into signal blocks that can be modeled with lossy transmission line techniques. Lastly, the power blocks and signal blocks associated with the electrical circuits are analyzed in order to predict the noise performance within the electrical circuits.

Abstract: New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:

Abstract: A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied.

Abstract: An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.

Abstract: A CMOS pass gate receiver improves chip-to-chip communication speed for high speed chips. The high speed CMOS pass gate receiver is immune to overshoot or undershoot and can operate in a frequency greater than or equal to 400 Mhz.

Abstract: An electronic switch circuit switches out bad decoupling capacitors on a high speed integrated circuit chip. The circuit comprises a control device that operates in the subthreshold or off device state to detect leakage in a decoupling capacitor. This control device operates in a low impedance state if the capacitor is good and in a high impedance sate if the capacitor is bad. A feedback circuit is connected from an internal node of the capacitor to a gate of the control device so that once a state of the capacitor is detected it can be stored on the gate of the control device. A single external signal source shared by a group of capacitors activates the control device to detect leakage in the capacitor. The circuit operates to switch out capacitors that fail during normal operation.