Abstract: Methods and systems include establishing a connection between two agents, storing a transaction header for data packets being transmitted from one agent to the other, transmitting the packets, updating the transaction header after successful transmission of one or more packets, and re-transmitting the updated transaction header when a disconnect event occurs. The re-transmission of the updated transaction header allows for an efficient re-start or re-connect between the agents of a previously disconnected transmission in a computer network system.

Abstract: Methods and systems include establishing a connection between two agents, storing a transaction header for data packets being transmitted from one agent to the other, transmitting the packets, updating the transaction header after successful transmission of one or more packets, and re-transmitting the updated transaction header when a disconnect event occurs. The re-transmission of the updated transaction header allows for an efficient re-start or re-connect between the agents of a previously disconnected transmission in a computer network system.

Abstract: Method and apparatus are disclosed which increase resource efficiency by collapsing writebacks to a memory. In general the method and apparatus receive an address of a memory request and compare that address to addresses of writebacks stored in a memory controller in order to determine whether the memory request maps to the same memory line of the memory as a stored writeback. If (1) the memory request generates a writeback, and (2) the memory request maps to the same line in the main memory as one of the stored writebacks, then the writeback generated from the memory request may be collapsed with one of the stored writebacks, thus reducing the number of writes to the main memory.

Abstract: A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

Abstract: A method used by a first memory controller to prevent deadlock of requests to a memory having a first memory line is disclosed. The method includes the steps of (1) receiving a first memory request for the first memory line from a first bus, (2) receiving a second memory request for the first memory line from a second bus, (3) propagating the first memory request through to the second bus after the second memory request receiving step, (4) processing the second memory request by storing a first modified copy of the first memory line in the first memory controller, and (5) processing the first memory request by (a) storing a second modified copy of the first memory line in the first memory controller, and (b) transferring the second modified copy of the first memory line to a caching agent in order to satisfy the first memory request.

Abstract: A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.

Abstract: An arbitration parking apparatus and method for a split transaction bus is provided. Processor agent(s) and memory agent(s) are connected by a split transaction bus which includes an arbiter to control access to the split transaction bus. The arbitration parking scheme includes parking a memory agent if there is an outstanding request. If there is no outstanding request and neither a processor nor memory agent request, then the arbiter parks either a memory agent or a processor agent depending on system characteristics. By parking the agent to request access to the split transaction bus next, arbitration overhead is reduced.

Abstract: A system and method of establishing error precedence in a computer system which determine a first error to occur. The system determines the order of occurrence of errors in a computer system and includes error precedence modules which record and order errors that occur on a first bus with error that occur on a second bus. Diagnostic processing circuitry reads the errors stored within the error precedence modules and their order of occurrence and determines which bus the first error occurred on.