Patents by Inventor Byron Lovell Williams

Byron Lovell Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375540
    Abstract: A laminate embedded core and coil structure comprises a magnetic core embedded in a laminate structure that includes two types of laminates. A first laminate embeds the coils of the structure and a second laminate fills space between the magnetic core and the first laminate, as well as space below the magnetic core and lower surface of the first laminate. The first and second laminates form a laminate structure that protects and improves isolation of the magnetic components. Solder resist encloses the laminate structure, magnetic core and coils. The laminate embedded core and coil structure may be assembled on a transformer leadframe of various types using non-conductive paste.
    Type: Application
    Filed: April 26, 2021
    Publication date: December 2, 2021
    Inventors: Yuki Sato, Kenji Otake, Zhemin Zhang, Byron Lovell Williams, Dongbin Hou, Sombuddha Chakraborty
  • Publication number: 20210367030
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 25, 2021
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 11107883
    Abstract: Isolator structures for an integrated circuit with reduced effective parasitic capacitance. Disclosed embodiments include an isolator structure with parallel conductive elements forming a capacitor or inductive transformer, overlying a semiconductor structure including a well region of a first conductivity type formed within an tank region of a second conductivity type. The tank region is surrounded by doped regions and a buried doped layer of the first conductivity type, forming a plurality of diodes in series to the substrate. The junction capacitances of the series diodes have the effect of reducing the parasitic capacitance apparent at the isolator.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 31, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raja Selvaraj, Anant Shankar Kamath, Byron Lovell Williams, Thomas D. Bonifield, John Kenneth Arch
  • Patent number: 11024576
    Abstract: A semiconductor package includes a leadframe including a sensor coil between sensor coil leads and further including a plurality of die leads physically and electrically separated from the sensor coil, and a semiconductor die over the leadframe with die contacts electrically connected to the die leads. The semiconductor die includes a sensor operable to detect magnetic fields created by electrical current through the sensor coil, the semiconductor die operable to output a signal representative of the detected magnetic fields via the die leads. The semiconductor package further includes a dielectric underfill filling a gap between the sensor coil and the semiconductor die, and a dielectric mold compound covering the sensor coil and the dielectric underfill and at least partially covering the semiconductor die and the die leads.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Byron Lovell Williams, Thomas Dyer Bonifield
  • Publication number: 20200381342
    Abstract: In examples, a semiconductor package comprises a first conductive terminal; a second conductive terminal; a conductive pathway coupling the first and second conductive terminals, the conductive pathway configured to generate a magnetic field; a semiconductor die including a circuit configured to detect the magnetic field; and first and second polyimide layers positioned between the conductive pathway and the semiconductor die.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: YongSeok PARK, Makarand Ramkrishna KULKARNI, Ricky Alan JACKSON, Byron Lovell WILLIAMS, Thomas Dyer BONIFIELD
  • Patent number: 10847605
    Abstract: High voltage integrated circuit capacitors are disclosed. In an example arrangement, A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: November 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 10811492
    Abstract: A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Byron Lovell Williams, John Britton Robbins
  • Publication number: 20200251440
    Abstract: An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: April 21, 2020
    Publication date: August 6, 2020
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR
  • Patent number: 10707297
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 10679935
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Publication number: 20200168534
    Abstract: In some examples, a multi-chip module (MCM), comprises a first and a second die-attach pad (DAP); a first die comprising a first set of microelectronic devices; a second die comprising a first capacitor and a second capacitor; and a third die comprising a second set of microelectronic devices, where the first and second dies are positioned on the first DAP, and the third die is positioned on the second DAP. The first set of microelectronic devices couples to the first capacitor via a first inter-die connection and the second set of microelectronic devices couples to the second capacitor via a second inter-die connection.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Thomas Dyer BONIFIELD, Sreeram Subramanyam NASUM, Robert H. EKLUND, Jeffrey Alan WEST, Byron Lovell WILLIAMS, Elizabeth Costner STEWART
  • Publication number: 20200135841
    Abstract: A method of fabricating an integrated circuit includes applying photoresist to a MESA dielectric layer of a semiconductor structure, to generate a photoresist layer. The method also includes exposing the photoresist layer with a grayscale mask, to generate an exposed photoresist layer. The photoresist exposed layer includes a thick photoresist pattern in a first region, a thin photoresist pattern in a second region where a height of the thin photoresist pattern is less than half a height of the thick photoresist pattern, and a gap region between the thick photoresist pattern and the thin photoresist pattern.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: Jeffrey Alan West, Byron Lovell Williams, John Britton Robbins
  • Patent number: 10629562
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Jason Chien, Byron Lovell Williams, Jeffrey Alan West, Anderson Li, Arvin Nono Verdeflor
  • Publication number: 20200027848
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Application
    Filed: July 30, 2019
    Publication date: January 23, 2020
    Inventors: THOMAS DYER BONIFIELD, JEFFREY ALAN WEST, BYRON LOVELL WILLIAMS
  • Publication number: 20200013713
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Patent number: 10418320
    Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: September 17, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. West, Byron Lovell Williams, David Leonard Larkin, Weidong Tian
  • Patent number: 10366958
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Patent number: 10349526
    Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: July 9, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Byron Lovell Williams, Asad Mahmood Haider, Licheng M. Han
  • Publication number: 20190206812
    Abstract: A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: THOMAS DYER BONIFIELD, JEFFREY ALAN WEST, BYRON LOVELL WILLIAMS
  • Publication number: 20190206828
    Abstract: An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 4, 2019
    Inventors: Honglin GUO, Jason CHIEN, Byron Lovell WILLIAMS, Jeffrey Alan WEST, Anderson LI, Arvin Nono VERDEFLOR