Patents by Inventor Byron N. Burgess

Byron N. Burgess has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8859168
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Publication number: 20110256644
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Application
    Filed: June 23, 2011
    Publication date: October 20, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Patent number: 7972753
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Publication number: 20110045388
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Application
    Filed: November 1, 2010
    Publication date: February 24, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Patent number: 7883822
    Abstract: In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein the metallic layer has tapered edges with a graded transparency. The lithographic mask, along with etching processes may be used to transfer a pattern 450a into a layer of a semiconductor device.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: February 8, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Byron N. Burgess, Stuart M. Jacobsen
  • Patent number: 7838178
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: November 23, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Publication number: 20090104540
    Abstract: In one aspect there is provided a gray scale lithographic mask that comprises a transparent substrate and a metallic layer located over the substrate, wherein the metallic layer has tapered edges with a graded transparency. The lithographic mask, along with etching processes may be used to transfer a pattern 450a into a layer of a semiconductor device.
    Type: Application
    Filed: October 17, 2007
    Publication date: April 23, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Byron N. Burgess, Stuart M. Jacobsen
  • Publication number: 20090047583
    Abstract: Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone.
    Type: Application
    Filed: August 13, 2007
    Publication date: February 19, 2009
    Applicant: Micron Technology, Inc.
    Inventors: Byron N. Burgess, William A. Stanton, Zhong Shi
  • Patent number: 7419865
    Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: September 2, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Byron N. Burgess
  • Patent number: 7279419
    Abstract: Methods of forming a contact structure for semiconductor assemblies are described. One method provides process steps to create an inner dielectric isolation layer after the contact region is protected, which is followed by the formation of the self-aligned contact structures. A second method provides process steps to create an inner dielectric isolation layer after the self-aligned contact structures are formed.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: October 9, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hyun T. Kim, Byron N. Burgess
  • Patent number: 7268384
    Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: September 11, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Byron N. Burgess
  • Patent number: 7229724
    Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns have unresolvable patterns formed in the periphery areas of the reticle patterns. The unresolvable patterns are non-transparent with respect to patterning radiation. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: June 12, 2007
    Assignee: Micron Technology, Inc.
    Inventors: William J. Baggenstoss, Byron N. Burgess, Erik Byers, William A. Stanton
  • Patent number: 7008843
    Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: March 7, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Byron N. Burgess
  • Patent number: 6921692
    Abstract: The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: July 26, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Kunal R. Parekh, Byron N. Burgess
  • Patent number: 6854106
    Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have sub-resolution patterns or a transmissive block fill formed in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: February 8, 2005
    Assignee: Micron Technology, Inc.
    Inventors: William J. Baggenstoss, Byron N. Burgess, Erik Byers, William A. Stanton
  • Patent number: 6818359
    Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have transmission patterns etched in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: November 16, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Byron N. Burgess, William A. Stanton
  • Publication number: 20040044982
    Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have sub-resolution patterns or a transmissive block fill formed in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventors: William J. Baggenstoss, Byron N. Burgess, Erik Byers, William A. Stanton
  • Publication number: 20040043304
    Abstract: Reticles having reticle patterns suitable for reducing edge of array effects are provided. The reticle patterns may have transmission patterns etched in the periphery areas of the reticle patterns. Systems incorporating the reticles are also provided. Additionally, methods of forming and using the reticles are provided. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that is will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 4, 2004
    Inventors: Byron N. Burgess, William A. Stanton