Patents by Inventor Byron Williams

Byron Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240122180
    Abstract: Disclosed is a fungicidal composition comprising (a) at least one compound selected from the compounds of Formula 1, including all geometric and stereoisomers, tautomers, A-oxides, and salts thereof, wherein E, L, J, A and T are as defined in the disclosure; and (b) at least one additional fungicidal compound. Also disclosed is a method for controlling plant diseases caused by fungal plant pathogens comprising applying to the plant or portion thereof, or to the plant seed, a fungicidally effective amount of a compound of Formula 1, an A-oxide, or salt thereof (e.g., as a component in the aforesaid composition). Also disclosed is a composition comprising: (a) at least one compound selected from the compounds of Formula 1 described above, A-oxides, and salts thereof; and at least one invertebrate pest control compound or agent.
    Type: Application
    Filed: March 11, 2021
    Publication date: April 18, 2024
    Inventors: Robert James PASTERIS, Travis Chandler MCMAHON, Hengbin WANG, Alvin Donald CREWS, JR., Liana HIE, Earl William REED, Srinivas CHITTABOINA, Ravisekhara P. REDDY, Srinivasa Rao UPPALAPATI, Yuzhong CHEN, Byron VEGA-JIMENEZ
  • Patent number: 11961879
    Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
  • Publication number: 20240095645
    Abstract: A method of generating customizable goal representation is disclosed. A request from a user to view a goal representation is received. A flexible goal ontology is accessed that comprises one or more goal entities, one or more goal relationships between the goal entities, or one or more goal properties, the one or more goal properties including one or more metadata attributes relating to the one or more goal entities. A set of mapping rules is obtained that defines mappings between one or more goals. The set of mapping rules is evaluated to assemble a customized goal representation tailored to the user. The customized goal representation is updated based on a revaluation of the mapping rules affected by changes to the one or more goal entities, the one or more goal relationships, or the one or more properties.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 21, 2024
    Inventors: Sven Martin Andreas Elfgren, Friedrich I. Riha, Elliot Piersa Dahl, Eric Koslow, Nicole Jensen McMullin, Natasha Hede, Connie Lynn Chen, Alexa Jean Kriebel, Chije Wang'ati, JR., Megan McGowan, Ami Tushar Bhatt, Jeffrey Ryan Gurr, Tyler Kowalewski, Rahul Rangnekar, Byron Sha Yang, Jerry Wu, Ricky Rizal Zein, Romain Beauxis, Adnan Chowdhury, Priya Balasubramanian, Gilles Yvetot, Shaylan Hawthorne, Adnan Pirzada, Matthew Michael Parides, Jenna Nicole Soojin Lee, Ian William Richard, Laura Elizabeth Pearson, Christian Nguyen, Tovin Thomas, Adam Carter, David Achee, David Christopher Sally, Miranda Howitt, Vincent Yao, Seth Goldenberg, Aimee Jin Peng, William Qingdong Yan, Matthew Stephen Wysocki, Michael Ryan Shohoney, Ryan Maas, Asha Camper Singh, Leonardo Faria, Elliot Piersa Dahl
  • Publication number: 20230369198
    Abstract: The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a package includes first and second IC dice. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is on a substrate. The capacitor includes a bottom plate over the substrate and a top plate over the bottom plate. The polyimide layer is at least partially over the top plate. A distance from a top surface of the top plate to a bottom surface of the polyimide layer is at least 30 % of a distance from a top surface of the bottom plate to a bottom surface of the top plate. A signal path, including the capacitor, is electrically coupled between the first circuit and a second circuit in the second IC die, which does not include a galvanic isolation capacitor in the signal path.
    Type: Application
    Filed: September 28, 2022
    Publication date: November 16, 2023
    Inventors: Elizabeth Stewart, Jeffrey Alan West, Byron Williams, Pijush Kanti Ghosh
  • Publication number: 20230268377
    Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
  • Patent number: 11688760
    Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: June 27, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
  • Publication number: 20230058511
    Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.
    Type: Application
    Filed: August 23, 2021
    Publication date: February 23, 2023
    Inventors: Jeffrey West, Mrinal Das, Byron Williams, Thomas Bonifield, Maxim Franke
  • Patent number: 11119631
    Abstract: Systems and methods to generate a playlist based on content meta data. In one embodiment, a method includes: receiving user-defined parameters; generating a playlist comprising a plurality of content portions, the generating comprising selecting the plurality of content portions from a data repository based on the user-defined parameters and further based on meta data for content stored in the data repository; and providing the playlist for display on a user device.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: September 14, 2021
    Assignee: Leaf Group Ltd.
    Inventors: Byron William Reese, Monica Winn Landers, Brian Andrew Dillon
  • Patent number: 11069627
    Abstract: A semiconductor die includes a plurality of layers, the plurality of layers having a top surface. A scribe seal is located in the plurality of layers and includes a first metal stack having a first metal layer located proximate the top surface. A trench is located in at least one layer of the plurality of layers. The trench extends from the top surface of the plurality of layers and is located a distance from the first metal stack. An electrical insulating layer is located on the top surface. The electrical insulating layer covers at least a portion of the top surface adjacent the first metal layer and extends a distance from the top surface of the first metal layer.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas D. Bonifield, Jeffrey A. West, Byron Williams, Honglin Guo
  • Patent number: 10926362
    Abstract: A remanufactured piston for an internal combustion engine includes a crown and a skirt. A piston body includes a first piston body end within the crown and an opposite second piston body end. The crown further includes an annular crown body having an annular crown body edge. The first piston body end further includes an annular piston body edge. The annular piston body edge and the annular crown body edge form a joint, and a metallurgical bond attaches the annular crown body to the piston body at the joint.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 23, 2021
    Assignee: Caterpillar Inc.
    Inventors: Kegan Jon Luick, Kevin Byron Williams, Nguyenbao Huynh Chu, Christopher Anthony Kinney
  • Publication number: 20200189045
    Abstract: A remanufactured piston for an internal combustion engine includes a crown and a skirt. A piston body includes a first piston body end within the crown and an opposite second piston body end. The crown further includes an annular crown body having an annular crown body edge. The first piston body end further includes an annular piston body edge. The annular piston body edge and the annular crown body edge form a joint, and a metallurgical bond attaches the annular crown body to the piston body at the joint.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Applicant: Caterpillar Inc.
    Inventors: Kegan Jon Luick, Kevin Byron Williams, Nguyenbao Huynh Chu, Christopher Anthony Kinney
  • Patent number: 10546821
    Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Licheng Marshal Han, Michael Andrew Serafin, Byron Williams, Sandra Rodriguez Varela, Salvatore Pavone
  • Publication number: 20190351213
    Abstract: An example patient line dislodgement detection device includes a body having a plurality of openings. The plurality of openings are each configured to receive a tubing line therethrough. The device is configured such that a force applied to a tubing line causes the body to restrict fluid flow through the tubing line. During use, the tubing line is received through the body of the dislodgement device. Fluid flow is restricted by the dislodgement device through the tubing line in response to application of a force on the tubing line. A dislodgement condition can be detected based on restricting the fluid flow through the tubing line.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventor: Byron William Larson
  • Patent number: 10398857
    Abstract: A patient line dislodgement detection device and method. An example device includes a body having an entrance and an exit. The entrance and the exit are each configured to receive a tubing line therethrough. Applying a force to a tubing line causes the body to restrict fluid flow through the tubing line, thereby indicating a dislodgement condition. An example method includes receiving a tubing line through a dislodgement device. The method also includes restricting fluid flow by the dislodgment device through the tubing line in response to application of a force on the tubing line. The method also includes detecting a dislodgment condition based on restricting the fluid flow through the tubing line.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 3, 2019
    Assignee: Toltec Ventures, LLC
    Inventor: Byron William Larson
  • Publication number: 20190129587
    Abstract: Systems and methods to generate a playlist based on content meta data. In one embodiment, a method includes: receiving user-defined parameters; generating a playlist comprising a plurality of content portions, the generating comprising selecting the plurality of content portions from a data repository based on the user-defined parameters and further based on meta data for content stored in the data repository; and providing the playlist for display on a user device.
    Type: Application
    Filed: December 24, 2018
    Publication date: May 2, 2019
    Inventors: Byron William Reese, Monica Winn Landers, Brian Andrew Dillon
  • Patent number: 10162486
    Abstract: Systems and methods to generate a playlist based on content meta data. In one embodiment, a method includes: receiving user-defined parameters; generating a playlist comprising a plurality of content portions, the generating comprising selecting the plurality of content portions from a data repository based on the user-defined parameters and further based on meta data for content stored in the data repository; and providing the playlist for display on a user device.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: December 25, 2018
    Assignee: LEAF GROUP LTD.
    Inventors: Byron William Reese, Monica Winn Landers, Brian Andrew Dillon
  • Patent number: 9893008
    Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan, David Larkin, Dhaval Atul Saraiya
  • Patent number: 9793106
    Abstract: It has been discovered that poor TDDB reliability of microelectronic device capacitors with organic polymer material in the capacitor dielectric is due to water molecules infiltrating the organic polymer material when the microelectronic device is exposed to water vapor in the operating ambient. Water molecule infiltration from water vapor in the ambient is effectively reduced by a moisture barrier comprising a layer of aluminum oxide formed by an atomic layer deposition (ALD) process. A microelectronic device includes a capacitor with organic polymer material in the capacitor dielectric and a moisture barrier with a layer of aluminum oxide formed by an ALD process.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: October 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Honglin Guo, Tim A. Taylor, Jeff A. West, Ricky A. Jackson, Byron Williams
  • Patent number: 9756885
    Abstract: The relay race gloves are provided to each runner participating in the relay race. That being said, there are a plurality of relay race gloves included, and each relay race glove is able to detect the presence of one another via a contact sensor. The contact sensor is ideally provided on a palm surface of the respective relay race glove such that during a relay race the two runners would simply touch each others hands in a manner consistent with a palm-to-palm clap in order for the contact sensors to detect one another, and initiate an alarm sequence. Each relay race glove includes a processing member that is wired to the contact sensor. The processing member is also wired to a transmitter, a receiver, a powering member, and a speaker.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 12, 2017
    Inventors: Byron Williams, Darryl Lewis
  • Publication number: 20170033057
    Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.
    Type: Application
    Filed: October 14, 2016
    Publication date: February 2, 2017
    Inventors: Licheng Marshal Han, Michael Andrew Serafin, Byron Williams, Sandra Rodriguez Varela, Salvatore Pavone