Patents by Inventor Byung-Chan RYU
Byung-Chan RYU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240154073Abstract: According to embodiments, a light-emitting display device includes a light-emitting diode that emits blue light and green light, a color conversion layer on the light-emitting diode, and a scattering absorption layer disposed between the color conversion layer and the light-emitting diode and that transmits blue light and green light.Type: ApplicationFiled: September 12, 2023Publication date: May 9, 2024Applicant: Samsung Display Co., LTD.Inventors: Gak Seok LEE, Byung-Chul KIM, Jang Wi RYU, Jae Min SEONG, Keun Chan OH, Sang Hun LEE, HALIM JI
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Patent number: 11973960Abstract: A video encoding/decoding apparatus according to the present invention acquires motion vector refinement information, performs motion compensation on the basis of a motion vector of a current block, refines the motion vector of the current block using at least one or both of the motion vector refinement information and the output of the motion compensation, and performs motion compensation using the refined motion vector.Type: GrantFiled: June 9, 2022Date of Patent: April 30, 2024Assignee: INTELLECTUAL DISCOVERY CO., LTD.Inventors: Yong Jo Ahn, Dong Gyu Sim, Ho Chan Ryu, Seanae Park, Byung Tae Oh, Byung Cheol Song
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Patent number: 11804528Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain pattern on the substrate, the source/drain pattern being at a side of the gate structure, a source/drain contact filling on and connected to the source/drain pattern, an entire top surface of the source/drain contact filling being lower than a top surface of the gate structure, and a connection contact directly on and connected to the source/drain contact filling, a top surface of the connection contact being higher than the top surface of the gate structure.Type: GrantFiled: May 20, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang Young Kim, Byung Chan Ryu, Da Un Jeon
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Patent number: 11362211Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: GrantFiled: December 30, 2020Date of Patent: June 14, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
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Publication number: 20220085179Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain pattern on the substrate, the source/drain pattern being at a side of the gate structure, a source/drain contact filling on and connected to the source/drain pattern, an entire top surface of the source/drain contact filling being lower than a top surface of the gate structure, and a connection contact directly on and connected to the source/drain contact filling, a top surface of the connection contact being higher than the top surface of the gate structure.Type: ApplicationFiled: May 20, 2021Publication date: March 17, 2022Inventors: Sang Young KIM, Byung Chan RYU, Da Un JEON
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Publication number: 20210126128Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: ApplicationFiled: December 30, 2020Publication date: April 29, 2021Inventors: Sang Young KIM, Deok Han BAE, Byung Chan RYU, Da Un JEON
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Patent number: 10886404Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: GrantFiled: July 17, 2019Date of Patent: January 5, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
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Patent number: 10593671Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.Type: GrantFiled: June 20, 2018Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Deok-Han Bae, Sang-Young Kim, Byung-Chan Ryu, Jong-Ho You, Da-Un Jeon
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Patent number: 10529859Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.Type: GrantFiled: May 24, 2018Date of Patent: January 7, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Byung Chan Ryu, Jong Ho You, Hyung Jong Lee
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Publication number: 20190341492Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: ApplicationFiled: July 17, 2019Publication date: November 7, 2019Inventors: Sang Young KIM, Deok Han BAE, Byung Chan RYU, Da Un JEON
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Patent number: 10374085Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: GrantFiled: June 5, 2018Date of Patent: August 6, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
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Patent number: 10361159Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.Type: GrantFiled: November 22, 2017Date of Patent: July 23, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
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Publication number: 20190148538Abstract: A semiconductor device includes a lower interlayer insulating film including a first trench and a second trench adjacent each other; a first gate structure within the first trench and extending in a first direction; a second gate structure within the second trench and extending in the first direction; a source/drain adjacent the first gate structure and the second gate structure; an upper interlayer insulating film on the lower interlayer insulating film; and a contact connected to the source/drain, the contact in the upper interlayer insulating film and the lower interlayer insulating film, wherein the contact includes a first side wall and a second side wall, the first side wall of the contact and the second side wall of the contact are asymmetric with each other, and the contact does not vertically overlap the first gate structure and the second gate structure.Type: ApplicationFiled: May 24, 2018Publication date: May 16, 2019Inventors: Byung Chan Ryu, Jong Ho You, Hyung Jong Lee
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Publication number: 20190148374Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.Type: ApplicationFiled: June 20, 2018Publication date: May 16, 2019Inventors: DEOK-HAN BAE, SANG-YOUNG KIM, BYUNG-CHAN RYU, JONG-HO YOU, DA-UN JEON
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Publication number: 20190148547Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.Type: ApplicationFiled: June 5, 2018Publication date: May 16, 2019Inventors: Sang Young KIM, Deok Han BAE, Byung Chan RYU, Da Un JEON
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Publication number: 20190051566Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.Type: ApplicationFiled: October 17, 2018Publication date: February 14, 2019Inventors: Sung-Min Kim, Ji-Su Kang, Byung-Chan Ryu, Jae-Hyun Park, Yu-Ri Lee, Dong-Ho Cha
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Patent number: 10147650Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.Type: GrantFiled: July 15, 2016Date of Patent: December 4, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Min Kim, Ji-Su Kang, Byung-Chan Ryu, Jae-Hyun Park, Yu-Ri Lee, Dong-Ho Cha
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Publication number: 20180286808Abstract: A semiconductor device includes a substrate having a plurality of fins protruding therefrom and an active region on the fins. The device further includes a contact including a conductive region having a concave portion defining an upper portion and a lower portion of the conductive region, an interlayer insulating layer on the active region, and a side insulating layer interposed between the interlayer insulating layer and the lower portion of the conductive region.Type: ApplicationFiled: November 22, 2017Publication date: October 4, 2018Inventors: Jong Ho You, Sang Young Kim, Byung Chan Ryu
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Publication number: 20170018464Abstract: A semiconductor device includes a first fin-type pattern and a second fin-type pattern which protrude upwardly from an upper surface of a field insulating film and extend in a first direction. A gate structure intersects the first fin-type pattern and the second fin-type pattern. A first epitaxial layer is on the first fin-type pattern on at least one side of the gate structure, and a second epitaxial layer is on the second fin-type pattern on at least one side of the gate structure. A metal contact covers outer circumferential surfaces of the first epitaxial layer and the second epitaxial layer. The first epitaxial layer contacts the second epitaxial layer.Type: ApplicationFiled: July 15, 2016Publication date: January 19, 2017Inventors: Sung-Min KIM, Ji-Su KANG, Byung-Chan RYU, Jae-Hyun PARK, Yu-Ri LEE, Dong-Ho CHA