Abstract: The present disclosure relates to a lithium secondary battery in which an abnormal voltage drop phenomenon is improved. The lithium secondary battery comprises a negative electrode comprising a negative electrode active material, a positive electrode comprising a positive electrode active material represented by Formula 1, a separator disposed between the positive electrode and the negative electrode, and a non-aqueous electrolyte solution, wherein the non-aqueous electrolyte solution comprises a lithium salt, a non-aqueous organic solvent, a compound represented by Formula 2 as a first additive, and lithium difluorophosphate as a second additive: LiaNixCOyM1zM2wO2??[Formula 1] wherein all the variables are described herein.

Abstract: The present disclosure provides a non-aqueous electrolyte including an additive for a non-aqueous electrolyte represented by Formula 1 below: wherein, R1 to R5 may each independently be any one selected from the group consisting of H, an alkenyl group having 2 to 20 carbon atoms, an alkynyl group having 2 to 20 carbon atoms, an alkoxy group having 1 to 20 carbon atoms, a cycloalkyl group having 3 to 12 carbon atoms, a cycloalkenyl group having 3 to 12 carbon atoms, and a nitrile group.

Abstract: The present disclosure discloses a flat substrate heating apparatus including a module support plate having a plurality of unit module regions placed on an upper surface thereof; a plurality of laser light source modules having a plurality of laser light source devices and seated on unit module regions of the module support plate, respectively; a power supply board placed below the module support plate and configured to supply power to the laser light source module; and an electrode terminal electrically connecting the laser light source module and the power supply board while detachably securing them to upper and lower surfaces of the module support plate.

Abstract: The present disclosure provides substrate heat-treating apparatus including a process chamber in which a flat substrate to be heat treated is placed, the process chamber comprising a beam irradiating plate placed below the flat substrate and an infrared transmitting plate placed above the flat substrate; a beam irradiating module for irradiating a laser beam to a lower surface of the flat substrate through the beam irradiating plate; and a gas circulation cooling module for spraying a cooling gas to an upper surface of the infrared transmitting plate, thereby cooling the infrared transmitting plate.

Abstract: A curing apparatus and a curing method are provided. The curing apparatus comprises: a chamber, configured for accommodating a substrate provided with a polyimide adhesive; an air extracting unit, configured for evacuating the chamber; and a heating unit, configured for performing a first heating on the substrate in the case that a first predetermined pressure is reached in the chamber during a evacuating process of the air extracting unit so as to remove organic gases from the polyimide adhesive, and performing a second heating on the substrate after the first heating so as to cure the polyimide adhesive.

Abstract: A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable agent; secondly, a whole layer of film (2) is formed on the complementary film pattern (1); and thirdly, the desired film pattern (201) is obtained by removing the complementary film pattern (1). The preparation method can simplify the production process and reduce the production cost of the film patterns.

Abstract: A curing apparatus and a curing method are provided. The curing apparatus comprises: a chamber, configured for accommodating a substrate provided with a polyimide adhesive; an air extracting unit, configured for evacuating the chamber; and a heating unit, configured for performing a first heating on the substrate in the case that a first predetermined pressure is reached in the chamber during a evacuating process of the air extracting unit so as to remove organic gases from the polyimide adhesive, and performing a second heating on the substrate after the first heating so as to cure the polyimide adhesive.

Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

Abstract: A method for preparing film patterns; firstly, a complementary film pattern (1) to a desired film pattern (201) is prepared on a substrate (3) with an erasable agent; secondly, a whole layer of film (2) is formed on the complementary film pattern (1); and thirdly, the desired film pattern (201) is obtained by removing the complementary film pattern (1). The preparation method can simplify the production process and reduce the production cost of the film patterns.

Abstract: A method for manufacturing an array substrate includes: forming a shielding layer, an insulating buffer layer, active layers, a gate insulating layer and NMOS gate electrodes in a display area and a drive area on a substrate in sequence; forming a PMOS gate electrode in the drive area on the foregoing substrate, in which the NMOS gate electrodes and the PMOS gate electrode are provided on the same layer; meanwhile forming a first through hole in a common electrode connecting area, in which the first through hole is configured to connect the shielding layer and a source/drain electrode layer; forming an intermediate insulating layer on the foregoing substrate, forming a second through hole in the common electrode connecting area and third through holes in the display area and the drive area, in which the second through hole is formed at a same position as the first through hole and configured to connect the shielding layer and a source/drain electrode layer, and the third through holes are configured to connec

Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.

Abstract: A method for manufacturing an array substrate includes: forming a shielding layer, an insulating buffer layer, active layers, a gate insulating layer and NMOS gate electrodes in a display area and a drive area on a substrate in sequence; forming a PMOS gate electrode in the drive area on the foregoing substrate, in which the NMOS gate electrodes and the PMOS gate electrode are provided on the same layer; meanwhile forming a first through hole in a common electrode connecting area, in which the first through hole is configured to connect the shielding layer and a source/drain electrode layer; forming an intermediate insulating layer on the foregoing substrate, forming a second through hole in the common electrode connecting area and third through holes in the display area and the drive area, in which the second through hole is formed at a same position as the first through hole and configured to connect the shielding layer and a source/drain electrode layer, and the third through holes are configured to connec

Abstract: A thin film transistor is provided, which comprises at least an active layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the active layer and spaced apart from each other; a channel is defined in the active layer between the source electrode and the drain electrode; edges of the active layer are aligned with outer edges of the source electrode and the drain electrode, the outer edge of the source electrode is an edge of the source electrode opposite to the drain electrode, and the outer edge of the drain electrode is an edge of the drain electrode opposite to the source electrode. Also, a method of manufacturing a thin film transistor is provided.

Abstract: A thin film transistor is provided, which comprises at least an active layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are located on the active layer and spaced apart from each other; a channel is defined in the active layer between the source electrode and the drain electrode; edges of the active layer are aligned with outer edges of the source electrode and the drain electrode, the outer edge of the source electrode is an edge of the source electrode opposite to the drain electrode, and the outer edge of the drain electrode is an edge of the drain electrode opposite to the source electrode. Also, a method of manufacturing a thin film transistor is provided.

Abstract: The present invention relates to an AAL-2/AAL-5 processing apparatus which is capable of simultaneously processing AAL-2 and AAL-5 cells transmitted through multiple virtual channels between a base station (BTS) and a base station controller(BSC).