Patents by Inventor Byung-Deok Yoo

Byung-Deok Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030136513
    Abstract: There is provided a semiconductor manufacturing apparatus comprising: a cassette station 16 in which wafers 18 are loaded; a stand-by conveying robot 10 for taking the wafers 18 out of the cassette station 16; a load lock chamber 12 in which the wafers 18 taken by the stand-by conveying robot 10 are accommodated; and a reaction chamber 14 placed in contact with the load lock chamber 12, the reaction chamber 14 having a shuttle blade 20 for drawing the wafers accommodated in the load lock chamber out of the load lock chamber 12 in a vacuum state and loading etched wafers in the load lock chamber, a rotary robot 26 for rotatively transferring the wafers taken out of the load lock chamber to be placed on the shuttle blade 20, and a heater stage 24 for etching the wafers transferred by the rotary robot 26 using a plasma generator 28, in which a pre-heating part 22 is placed above the shuttle blade 20, for pre-heating the wafers transferred into the reaction chamber 14 from the load lock chamber 12 before they are
    Type: Application
    Filed: January 22, 2002
    Publication date: July 24, 2003
    Inventors: Soon Ho Lee, Seong Sook Yi, Jin Seok Park, Sung Up Yoon, Jong Sik Kim, Byung Chul Kim, Byung Deok Yoo
  • Patent number: 5089436
    Abstract: This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.
    Type: Grant
    Filed: May 2, 1990
    Date of Patent: February 18, 1992
    Assignee: Samsung Semiconductor and Telecommunications Co., Ltd.
    Inventors: Jung-In Hong, Byung-Deok Yoo, Tae-Hyuk Ahn