Patents by Inventor Byung-Do Yang

Byung-Do Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299406
    Abstract: The battery pack includes at least one battery module having a plurality of battery cells; a pack tray having a module mounting portion configured to mount one or more of the battery modules and extending in a horizontal direction, and a side cover portion extending upwardly from an outer periphery of the module mounting portion to cover a side of the battery module; and at least one side plate coupled to any one or more of the module mounting portion and the side cover portion, provided on one or both sides of the battery module, having a plurality of through-holes, and configured to block at least one surface of the battery module when the battery module is expanded.
    Type: Application
    Filed: January 27, 2022
    Publication date: September 21, 2023
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Chang-Hyeon YANG, Hae-Jin KIM, Byung-Do JANG
  • Patent number: 11671101
    Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: June 6, 2023
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jae-Mun Oh, Byung-Do Yang, Jung-Ho Kim
  • Publication number: 20230170553
    Abstract: Discussed is a battery pack, which may include a battery module including a battery cell and having a cooling pipe unit including a coolant flow path for cooling the battery cell, a pack case configured to accommodate the battery module, a coolant inflow and outflow pipe configured to supply a coolant to the coolant flow path and to discharge the coolant from the coolant flow path to an outside of the pack case, a first sealing unit between the coolant inflow and outflow pipe and the pack case, and a second sealing unit between the coolant inflow and outflow pipe and the cooling pipe unit.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 1, 2023
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Chang-Hyeon YANG, Hae-Jin KIM, Byung-Do JANG
  • Publication number: 20230097393
    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.
    Type: Application
    Filed: November 8, 2021
    Publication date: March 30, 2023
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Haeng CHO, Byung-Do YANG, Sooji NAM, Jaehyun MOON, Jae-Eun PI, Jae-Min KIM
  • Publication number: 20230102625
    Abstract: Provided is a static random-access memory (SRAM) device.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 30, 2023
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Sung Haeng CHO, Byung-Do YANG, Sooji NAM, Jaehyun MOON, Jae-Eun PI, Jae-Min KIM
  • Publication number: 20220321127
    Abstract: Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.
    Type: Application
    Filed: September 8, 2021
    Publication date: October 6, 2022
    Inventors: Jae-Mun OH, Byung-Do YANG, Jung-Ho KIM
  • Patent number: 7920413
    Abstract: Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: April 5, 2011
    Assignees: Electronics & Telecommunications Research Institute, Cungbuk Nat'l Univ. Industry Academic Cooperation Foundation
    Inventors: Byoung-Gon Yu, Byung-Do Yang, Seung-Yun Lee, Sung-Min Yoon, Young Sam Park, Nam Yeal Lee
  • Publication number: 20080219047
    Abstract: Provided are an apparatus and method for writing data to a phase-change random access memory (PRAM) by using writing power calculation and data inversion functions, and more particularly, an apparatus and method for writing data which can minimize power consumption by calculating the power consumed while input original data or inverted data is written to a PRAM and storing the data consuming less power. A PRAM consumes a significant amount of power in order to store data in a memory cell since a large electric current is required to flow for a long period of time.
    Type: Application
    Filed: February 29, 2008
    Publication date: September 11, 2008
    Applicants: Electronics and Telecommunications Research Institute, Cungbuk National University Industry Academic Cooperation Foundation
    Inventors: Byoung-Gon YU, Byung-Do Yang, Seung-Yun Lee, Sung-Min Yoon, Young Sam Park, Nam Yeal Lee
  • Patent number: 6615398
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: September 2, 2003
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim
  • Publication number: 20030014721
    Abstract: The present invention relates to a ROM division method for reducing the size of a ROM in a direct digital frequency synthesizer (DDFS), which is used to synthesize a frequency in a communication system requiring fast frequency conversion. A ROM consuming most energy in the system, a modified Nicholas architecture is brought forth to reduce the size of ROM. In this modified Nicholas architecture, a ROM is divided into coarse ROM and fine ROM to convert phase to sine value. The present invention divides the coarse ROM and the fine ROM into quantized ROM and error ROM respectively. Then, value stored in each ROM is segmented in certain intervals and the minimum quantized value in each of the section is stored in the quantized ROM, while the difference between the original ROM value and the quantized ROM value is stored in the error ROM. This way, the size of a ROM can be reduced. Phase value inputted in a DDFS, a sine value is calculated by adding the four ROM values, i.e.
    Type: Application
    Filed: December 18, 2001
    Publication date: January 16, 2003
    Inventors: Hyun Kyu Yu, Seon-Ho Han, Mun Yang Park, Seong-Do Kim, Yong-Sik Youn, Lee-Sup Kim, Ki-Hyuk Sung, Byung-Do Yang, Young-Jun Kim