Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.

Abstract: A method for forming an isolation layer in a semiconductor device includes forming a trench in a semiconductor substrate, forming a first liner nitride layer on an exposed surface of the trench, forming a first high density plasma (HDP) oxide layer such that the first HDP oxide layer partially fills the trench to cover a bottom surface and a side surface of the trench and an upper surface of the first liner nitride layer, etching overhangs generated during the forming of the first HDP oxide layer by introducing a hydrofluoric acid (HF) solution into the semiconductor substrate, forming a second liner nitride layer over the first HDP oxide layer, removing the second liner nitride layer formed on the first HDP oxide layer while forming a second HDP oxide layer to fill the trench, and subjecting the second HDP oxide layer to planarization, so as to form a trench isolation layer.

Abstract: Provided are a method for fabricating a semiconductor device and a semiconductor device fabricated using the same. The method for fabricating a semiconductor device comprises forming gate stacks on a semiconductor substrate, forming gate spacers made of a dielectric material having a dielectric constant of 2 to 4, on the sides of the gate stacks, forming an interlayer dielectric film on the resulting structure and etching the interlayer dielectric film, thereby forming a landing plug contact hole, and filling the landing plug contact hole with a conductive material, thereby forming a landing plug contact.

Abstract: A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first liner nitride film is formed overlying the first sidewall oxide film. Second trenches have a predetermined depth and are formed in the semiconductor substrate at the peripheral circuit regions. A second sidewall oxide film is formed overlying the second trenches. An oxide film fills the first overlying second trenches. A second liner nitride film formed on the filling oxide film. The second liner nitride film is separated from the sidewalls of the first and second trenches.

Abstract: Provided is a semiconductor device having recess channel, comprising a semiconductor substrate having first and second trenches disposed to cross each other on both sides of an active region among adjoining regions between an active region and element-isolation films; a gate insulation film disposed on the semiconductor substrate of the active region; a first gate line disposed on the gate insulation film, and crossing the active region and overlapping with the first trench; and a second gate line disposed on the gate insulation film, and crossing the active region while overlapping with the second trench.

Abstract: A semiconductor device having step gates includes a semiconductor substrate including first regions having relatively low steps at both ends of an active region defined by trench isolation films and a second region having a relatively high step at a central part of the active region, a groove having a predetermined depth being formed at the central part of the second region, step gate stacks formed on the boundary between the first region and second region while exposing the groove of the second region, first impurity regions formed in the first regions exposed by the step gate stacks, and a second impurity region formed in the second region exposed by the step gate stacks while enclosing the groove of the second region.

Abstract: The present invention relates to a bit line barrier metal layer for a semiconductor device and a process for preparing the same, the process comprising: forming bit line contact on an insulation layer vapor-deposited on an upper part of a substrate so as to expose an ion implantation region; vapor-depositing a first barrier metal layer of a Ti film on the entire upper surface thereof; and vapor-depositing, on the upper part of the Ti film, a second barrier metal layer of a ZrB2 film having different upper and lower Boron concentrations, by RPECVD controlling the presence/absence of H2 plasma, wherein the barrier metal layer includes the Ti film, lower ZrB2 film and upper a ZrB2 film sequentially stacked between tungsten bit lines and ion implantation region of a semiconductor substrate.