Abstract: A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank.

Abstract: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

Abstract: Nonvolatile memory devices include an array of variable-resistance memory cells and a write driver electrically coupled to the array. The write driver is configured to drive a bit line in the array of variable-resistance memory cells with a stair-step sequence of at least two unequal bit line voltages during an operation to program a variable-resistance memory cell in said array. This stair-step sequence of at least two unequal bit line voltages includes a precharge voltage (e.g., Vcc-Vth) at a first step and a higher boosted voltage (e.g., Vpp-Vth) at a second step that follows the first step.

Abstract: A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.

Abstract: A nonvolatile memory device includes a memory cell array with a matrix of nonvolatile memory cells. The nonvolatile memory cells may store data using variable resistive elements. A plurality of bitlines are coupled to a plurality of nonvolatile memory cell arrays in the memory cell array. A column selection circuit selects among the bitlines in response to a column selection signal. A controller regulates a level of the column selection signal in response to a temperature signal from a temperature sensor. The temperature sensor may be configured to measure temperature outside the nonvolatile memory device to generate the temperature signal.

Abstract: A variable resistive memory device includes memory sectors, memory cells in each of the memory sectors, sub-wordlines including a first in signal communication with at least a first pair of the memory cells in a first sector and a second in signal communication with at least a second pair of the memory cells in a second sector, local bitlines where each is in signal communication a memory cell, a local bitline selecting signal generator in signal communication with local bitline selecting signal paths, a first local bitline selecting signal path in signal communication with a first pair of the local bitlines, and a second local bitline selecting signal path in signal communication with a second pair of the plurality of local bitlines, where a first of the first pair of local bitlines is in signal communication with a first of the first pair of the memory cells in the first sector and a second of the first pair of local bitlines is in signal communication with a second of the second pair of the memory cells in

Abstract: The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

Abstract: A nonvolatile memory device includes multiple memory blocks divided into multiple memory block groups. Each memory block group includes at least two memory blocks of the multiple memory blocks. The nonvolatile memory device also includes a main word line common to the memory blocks, and multiple sub-word lines corresponding to the memory blocks. Sub-word lines of the multiple sub-word lines located within the same memory block group are electrically connected to each other, and sub-word lines of the multiple sub-word lines located in different memory block are electrically isolated from each other.

Abstract: A variable resistive memory device includes a main wordline, a wordline connecting switch in signal communication with the main wordline, a sub-wordline in signal communication with the wordline connecting switch, and a variable resistive memory cell having a variable resistance in signal communication with a first terminal of a switching element, a second terminal of the switching element disposed in signal communication with the sub-wordline; and a method of controlling the voltage of a sub-wordline in a variable resistive memory device includes switchably passing a voltage from a main wordline to the sub-wordline, and substantially blocking forward current flow from the sub-wordline to a variable resistive memory cell of the device.

Abstract: A nonvolatile memory device may include a memory cell array with a plurality of nonvolatile memory cells arranged in an array of rows and columns. Each of a plurality of bit lines may be coupled to nonvolatile memory cells in a respective one of the columns of the array, and each of a plurality of column selection switches may be coupled to a respective one of the bit lines. A column decoder may be coupled to the plurality of column selection switches, and the column decoder may be configured to select a first one of the bit lines using a first column selection signal having a first signal level applied to a first one of the column selection switches. The column decoder may be further configured to select a second one of the bit lines using a second column selection signal having a second signal level applied to a second one of the column selection switches with the second signal level being different than the first signal level.

Abstract: A nonvolatile memory device using a variable resistive element is provided. The nonvolatile memory device may include a memory cell array which includes an array of multiple nonvolatile memory cells having variable resistance levels depending on data stored. Word lines may be coupled with each column of the nonvolatile memory cells. Local bit lines may be coupled with each row of the nonvolatile memory cells. Global bit lines may be selectively coupled with the multiple local bit lines.

Abstract: A phase-change memory device includes a semiconductor substrate, a bit line and a word line arranged on the semiconductor substrate to intersect each other, and a phase-change material strip interposed between the bit line and the word line and extending lengthwise in a direction that is substantially parallel to at least a portion of the word line.

Abstract: The invention provides a heat treatment apparatus, in which an intake valve (91a) is mounted on an ambient gas feed pipe (91) connected to a heating chamber (12), an exhaust valve (131a) is mounted on an exhaust pipe (131), and a pressure sensor (150) is provided on the heating chamber (12). Through the control of a control unit (80) connected to the pressure sensor (150), to the intake valve (91a) and to the exhaust valve (131a), the intake valve (91a) and the exhaust valve (131a) are opened or closed, thus supplying ambient gas into the heating chamber (12) or exhausting ambient gas from the cooling chamber (13) depending on an internal pressure of the heating chamber (12). Thus, the amount of ambient gas used in heat treating workpieces (1) is minimized and thus operational costs are reduced. It is possible to prevent accidents such as gas explosions as well as to reduce environmental contamination caused by the combustion of ambient gas.

Abstract: A multilevel nonvolatile memory device using a resistance material is provided. The multilevel nonvolatile memory device includes at least one multilevel memory cell and a read circuit. The at least one multilevel memory cell has a level of resistance that varies according to data stored therein. The read circuit first reads first bit data from the multilevel memory cell by providing a first read bias to the multilevel memory cell and secondarily reads second bit data from the multilevel memory cell by providing a second read bias to the multilevel memory cell. The second read bias varies according to a result of the first reading.

Abstract: A variable resistance memory device includes a variable resistance memory cell array including a plurality of variable resistance memory cells; a plurality of global word lines configured to drive the variable resistance memory cell array; and a plurality of local word line decoders. Each of the plurality of local word line decoders includes a first transistor having a gate connected to the global word line. A voltage greater than an operation voltage of one or more of the plurality of local word line decoders is applied to a selected one of the plurality of global word lines.

Abstract: A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.

Abstract: In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

Abstract: A multi-level nonvolatile memory device using variable resistive element with improved reliability of read operations is provided. A multi-level nonvolatile memory device comprises a multi-level memory which includes a resistance element, wherein the resistance level of the resistance element is variable depending on data stored in the multi-level memory cell, and a read circuit which provides the multi level memory cell with a read bias and performs a sensing operation in response to the read bias, wherein the read bias has at least two levels during a read cycle.

Abstract: A semiconductor memory device includes at least one write global bit line connected to a plurality of local bit lines and at least one read global bit line connected to the local bit lines. The phase-change memory device having the write global bit line and the read global bit line suppress coupling noise generated during a read-while-write operation.

Abstract: A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.