Patents by Inventor Byung-Gil Jeong

Byung-Gil Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070264757
    Abstract: A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 15, 2007
    Inventors: Jong-oh KWON, Woon-Bae Kim, In-sang Song, Ji-hyuk Lim, Suk-jin Ham, Byung-gil Jeong
  • Patent number: 7285865
    Abstract: A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 23, 2007
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jong-oh Kwon, Woon-bae Kim, In-sang Song, Ji-hyuk Lim, Suk-jin Ham, Byung-gil Jeong
  • Publication number: 20070020817
    Abstract: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.
    Type: Application
    Filed: June 7, 2006
    Publication date: January 25, 2007
    Inventors: Byung-gil Jeong, In-sang Song, Woon-bae Kim, Min-seog Choi, Suk-jin Ham, Ji-hyuk Lim
  • Publication number: 20070013058
    Abstract: A packaging chip formed with plural wafers. The packaging chip includes plural wafers stacked in order and plural interconnection electrodes directly connecting the plural wafers from an upper surface of an uppermost wafer of the plural wafers to the other wafers. At least one or more of the plural wafers mounts a predetermined circuit device thereon. Further, at least one or more wafers of the plural wafers have a cavity of a predetermined size. Meanwhile, the packaging chip further includes plural pads independently arranged on the upper surface of the uppermost wafer one another and electrically connected to the plural interconnection electrodes respectively. Accordingly, the present invention can enhance the performance and reliability of a packaging chip and improve fabrication yield.
    Type: Application
    Filed: July 6, 2006
    Publication date: January 18, 2007
    Inventors: Min-seog Choi, Kae-dong Back, In-sang Song, Woon-bae Kim, Byung-gil Jeong, Kyu-dong Jung
  • Publication number: 20070012655
    Abstract: A micro package, a multi-stack micro package, and a manufacture method therefor are provided. A micro package according to the present invention includes a device substrate for mounting a devices, being a circuit module; a protection cap for protecting the device; bonding substances which, formed by patterning on predetermined areas on the device substrate, bond the device substrate and the protection cap; layers formed on a portion of the device substrate and a portion of the protection cap and exterior sides of the bonding substances; vias which are formed by etching away another portion of the protection cap, and electrically connected to an upper surface of the device substrate through the bonding substances; under barrier metals (UBMs) formed on the vias; and solder bumpers, being connection terminals for an external signal, formed on the UBMs.
    Type: Application
    Filed: April 4, 2006
    Publication date: January 18, 2007
    Inventors: Jong-oh Kwon, Woon-bae Kim, In-sang Song, Ji-hyuk Lim, Suk-jin Ham, Byung-gil Jeong
  • Patent number: 7103256
    Abstract: Disclosed is a multi-core optical fiber block having a block base and a cover, each of which is formed having a tree-structured groove array, so as to allow respective optical fiber arrays to be seated in the corresponding respective groove arrays. The groove arrays comprises first sub-grooves having depth and pitches decreasing in magnitude as approaching from an input end of the block to an output end, and second sub-grooves formed alternately between the first sub-grooves and having the depths and pitches increasing in magnitude as approaching from the input end of the block to the output.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Chae Song, Byung-Gil Jeong
  • Patent number: 6953286
    Abstract: Disclosed is a ferrule for hermetically packaging optical fibers which includes: an opening provided along a longitudinal direction of the ferrule and having an optical-fiber cable passing there-through; the optical-fiber cable including a plurality of optical-fiber strands; a pair of soldering holes, each extending from a predetermined place on the outer peripheral surface of the ferrule to the through hole; and a pinhole positioned between the soldering holes and extending from a predetermined place on the outer peripheral surface of the ferrule to the through hole.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: October 11, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Gil Jeong, Oh-Dal Kwon
  • Patent number: 6795634
    Abstract: Disclosed is an optical fiber block having holding sub-blocks. The optical fiber block comprises: an optical fiber arrangement section having a V-groove array including a plurality of V-grooves; a stress-relieving recess section extending from the optical fiber arrangement section, the stress-relieving recess section having a flat surface on which a ribbon optical fiber is fixed, the flat surface being formed to be substantially lower than the lower ends of the V-grooves by etching; and at least one holding sub-block formed on a rear portion of the side edge of the flat surface of the stress-relieving recess section, so as to prevent the ribbon optical fiber placed on the flat surface from escaping out of the flat surface and guide the flow of epoxy resin injected toward the ribbon optical fiber.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Gil Jeong, Seung-Wan Lee, Hyun-Chae Song
  • Patent number: 6757471
    Abstract: The present invention discloses an optical-fiber-block assembly for minimizing stress concentration. The optical-fiber-block assembly is comprised of a fiber-alignment area mounted with a plurality of V-grooves at which optical fibers are disposed and a stress-relief-depth area extending from the fiber-alignment area and formed by etching the fiber-alignment area deeper by a predetermined amount, for relieving stress that is caused by the coating thickness of the fiber, wherein the fiber-alignment area further includes: (a) a first fiber-alignment area having a first V-grooves with a constant width for receiving the bare fibers, such that the first fiber-alignment area do not contact the external side of the bare fiber, and (b) a second fiber-alignment area having a second V-grooves with a constant width extending from the first V-grooves for receiving the bare fiber, wherein the width of the first V-grooves is substantially wider than the width of the second V-grooves.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: June 29, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Gil Jeong, Hyun-Chae Song, Seung-Wan Lee
  • Publication number: 20040042734
    Abstract: Disclosed is a ferrule for hermetically packaging optical fibers which includes: an opening provided along a longitudinal direction of the ferrule and having an optical-fiber cable passing there-through; the optical-fiber cable including a plurality of optical-fiber strands; a pair of soldering holes, each extending from a predetermined place on the outer peripheral surface of the ferrule to the through hole; and a pinhole positioned between the soldering holes and extending from a predetermined place on the outer peripheral surface of the ferrule to the through hole.
    Type: Application
    Filed: April 29, 2003
    Publication date: March 4, 2004
    Inventors: Byung-Gil Jeong, Oh-Dal Kwon
  • Publication number: 20030169995
    Abstract: Disclosed is a multi-core optical fiber block having a block base and a cover, each of which is formed having a tree-structured groove array, so as to allow respective optical fiber arrays to be seated in the corresponding respective groove arrays. The groove arrays comprises first sub-grooves having depth and pitches decreasing in magnitude as approaching from an input end of the block to an output end, and second sub-grooves formed alternately between the first sub-grooves and having the depths and pitches increasing in magnitude as approaching from the input end of the block to the output.
    Type: Application
    Filed: January 30, 2003
    Publication date: September 11, 2003
    Inventors: Hyun-Chae Song, Byung-Gil Jeong
  • Publication number: 20030133689
    Abstract: Disclosed is an optical fiber block having holding sub-blocks. The optical fiber block comprises: an optical fiber arrangement section having a V-groove array including a plurality of V-grooves; a stress-relieving recess section extending from the optical fiber arrangement section, the stress-relieving recess section having a flat surface on which a ribbon optical fiber is fixed, the flat surface being formed to be substantially lower than the lower ends of the V-grooves by etching; and at least one holding sub-block formed on a rear portion of the side edge of the flat surface of the stress-relieving recess section, so as to prevent the ribbon optical fiber placed on the flat surface from escaping out of the flat surface and guide the flow of epoxy resin injected toward the ribbon optical fiber.
    Type: Application
    Filed: November 27, 2002
    Publication date: July 17, 2003
    Inventors: Byung-Gil Jeong, Seung-Wan Lee, Hyun-Chae Song
  • Publication number: 20030081926
    Abstract: The present invention discloses an optical-fiber-block assembly for minimizing stress concentration. The optical-fiber-block assembly is comprised of a fiber-alignment area mounted with a plurality of V-grooves at which optical fibers are disposed and a stress-relief-depth area extending from the fiber-alignment area and formed by etching the fiber-alignment area deeper by a predetermined amount, for relieving stress that is caused by the coating thickness of the fiber, wherein the fiber-alignment area further includes: (a) a first fiber-alignment area having a first V-grooves with a constant width for receiving the bare fibers, such that the first fiber-alignment area do not contact the external side of the bare fiber, and (b) a second fiber-alignment area having a second V-grooves with a constant width extending from the first V-grooves for receiving the bare fiber, wherein the width of the first V-grooves is substantially wider than the width of the second V-grooves.
    Type: Application
    Filed: October 21, 2002
    Publication date: May 1, 2003
    Inventors: Byung-Gil Jeong, Hyun-Chae Song, Seung-Wan Lee